| 0847 | MC/Tower/Cold Plate = 24.7 / 31.9 / 137 mK, Still = 1.07 K / 0.11 mbar, G1/G2 = 165 / 162 mbar, 1K Pot = 1.70 K / 18 mbar, MB = 68.8% |
| 0906 | Fill LN trap Dewar |
| 0910 | Start one-shot test. Before this, MC = 24.8 mK, G1/G2/P1 = 163/160/0.10 mbar. |
| 0913 | Meant to apply heat to still, but accidentally applied to MC instead. Caught the mistake after a few minutes, allowed MC to cool. |
| 0927 | MC cools to min. 22.2 mK with Still = 5 mW / 0.11 mbar, G1 = 26 mbar, G2 (dump) = 76 mbar. Then MC temperature begins to rise. |
| 0931 | Stop one-shot with G2 (dump) = 83 mbar, restore circulation. MC = 25.0 mK. |
| 0933 | Open V14 to return all mix to circulation. After 5 minutes wtih P1 (dump) down to 7.5 mbar, close V14, restore normal circulation. |
| 0940 | Check pressure in LHe transfer tube vacuum jacket. Reads 1.0 mbar at Pfeiffer gauge. Includes large volumes of three bellows, so jacket pressure was probably above 10 mbar. We'll need to pump out the jacket I think before every transfer, and do the transfer within a few hours of pumpout. Between runs we should try to fix the transfer tube. |
| 1000 | Studying pulses with DCRC31-DIB1, DCRC33-DIB2, DCRC50-DIB3 configuration. See below. |
As with studies of DCRC31 yesterday, we only triggered on the phonon channel of interest and we did not look beyond a front end gain of 5. Unlike RevC boards (like 31), RevC.1 boards have a front end gain of 2^x for the selected value of x up to 3 (x=4 should act like x=1 x=0), so you can select and output gain of 1, 2, 4, 8. We usually kept a trigger threshold of 250 ADC Bins for all channels.
| Figure 1: DCRC 50 DIB 3: Phonon Channel A |
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| FrontEnd Gain of 5, Output Gain of 3, Driver Offset of +0.028, and Trigger Threshold of 250 |
| Figure 2: DCRC 50 DIB 3: Phonon Channel B |
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| FrontEnd Gain of 5, Output Gain of 4, Driver Offset of +0.042, and Trigger Threshold of 250 |
As with DCRC31, we found that phonon channels C and D were the noisiest channels (particularly D), and in particular we noted that most pulse on these channels had noisy “ripples” similar to those seen in the previous G106a run pulses (see note for examples).
| Figure 3: DCRC 50 DIB 3: Phonon Channel C |
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| FrontEnd Gain of 5, Output Gain of 3, Driver Offset of +0.018, and Trigger Threshold of 150 |
| Figure 4: DCRC 50 DIB 3: Phonon Channel D |
| Typical “good” pulse |
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| FrontEnd Gain of 5, Output Gain of 4, Driver Offset of +0.066, and Trigger Threshold of 250 |
| Table 1: Gains and Thresholds for DCRC50 in DIB3 |
| Channel | Front End Gain | Output Gain Set (Actual) | Driver Offset | Trigger Threshold |
| A | 5 | 3 (8) | +0.028 | 250 |
| B | 5 | 3 (8) | +0.042 | 50 |
| C | 5 | 3 (8) | +0.018 | 250 |
| D | 5 | 3 (8) | +0.066 | 250 |
The settings in Table 1 above, and the QET biases from Table 1 on 2015/06/09, were saved into the settings file I:\data\run053\dcrc50_dib3_0V_test.xml
During these studies, we noticed that many pulses were saturated, and that saturation levels changed with based on the output gain. These saturated pulses were not noticed when DCRC31 was in DIB3 (though that does not mean they were not present), but they were highly prevalent in the previous G106a run. Below includes a sample of these saturated pulses for phonon channel A on DIB3, with different gains applied.
| Figure 5: DCRC50 on DIB3, Phonon Channel A FG:1 OG:1 |
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| Figure 5: DCRC50 on DIB3, Phonon Channel A Feedback Gain:5 Output Gain:1 |
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| Figure 5: DCRC50 on DIB3, Phonon Channel A Feedback Gain:5 Output Gain:2 |
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| Figure 5: DCRC50 on DIB3, Phonon Channel A Feedback Gain:5 Output Gain:3 |
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| Figure 5: DCRC50 on DIB3, Phonon Channel A Feedback Gain:5 Output Gain:4 |
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| Table 2: Gains and Saturation values for DCRC50 in DIB3 |
| Channel | Front End Gain | Output Gain | Saturation Level (V) |
| A | 1 | 1 (2) | 0.22 |
| A | 5 | 1 (2) | 0.25 |
| A | 5 | 2 (4) | 0.50 |
| A | 5 | 3 (8) | 1.10 |
| A | 5 | 4 (1) | 0.10 |
| | | | |
| B | 1 | 1 (2) | 0.30 |
| B | 5 | 1 (2) | 0.35 |
| B | 5 | 2 (4) | 0.70 |
| B | 5 | 3 (8) | 0.55 |
| B | 5 | 4 (1) | 0.18 |
| | | | |
| C | 1 | 1 (2) | 0.19 |
| C | 5 | 1 (2) | 0.19 |
| C | 5 | 2 (4) | 0.40 |
| C | 5 | 3 (8) | 0.80 |
| C | 5 | 4 (1) | 0.11 |
| | | | |
| D | 1 | 1 (2) | 0.40 |
| D | 5 | 1 (2) | 0.44 |
| D | 5 | 2 (4) | 0.90 |
| D | 5 | 3 (8) | 1.20 |
| D | 5 | 4 (1) | 0.23 |
| 1330 | Commence data acquisition of DIB3 with DCRC50 attached using SQUID and QET settings determined with DCRC50: -/+0 V biases; one 10-minute file; no flashing; Phonon OR charge trigger at 250 ADC bins. Store data in directory I:\data\run053\20150610. |
| 1400 | Tc measurements on DIB2 (DCRC33). SQUIDs set, QET biases off, gains set to 1, apply 10 mVpp 100 Hz signal to all four QET lines and look for temperature region in which triangle-wave is distorted. Apply 30 to 55 μW to MC to warm tower to above 90 mK. Monitor with Tower thermometer. Both heating and cooling was done at a rate of about 4 mK/minute. |
| Tc measurements for DIB2 (DCRC33) - temperatures at Tower |
| | Temperature range in which waveform is distorted |
| Channel | During heating | During cooling |
| A | 79.9-81.5 mK | 81.2-82.4 mK |
| B | 84.5-84.7 mK | 85.0-85.8 mK |
| C | 84.5-86.4 mK | 85.0-86.9 mK |
| D | 76.7-79.2 mK | 77.3-79.4 mK |
These serve as a thermometry comparison with the Run 34 Tc measurements, the Tc measurement of pC2 from Run 35, and the Run 46 Tc measurements. It looks like in that run there was no tower thermometer, so the temperatures are MC temperatures.
| 1618 | Without changing DCRC configuration (DIB1-DCRC31, DIB2-DCRC33, DIB3-DCRC50) attempt to study pulse noise again when shielding DCRC 50, which usually does not have a front-side shield. During these studies, it is noted that the driver offset has changed for all the channels, except phonon channel B. The new driver offsets were as follows: +0.056 for A, +0.058 for B, +0.042 for C, +0.022 for D. It was also seen that shielding DCRC50 yielded no improvements in pulse noise or shape. Attempts were also made to use a grounding strip to affect the pulse noise. Connecting the grounding strip from the fridge support to the Ebox yielded no change in the pulse shape. Connecting the grounding strip from the fridge support to the DCRC50 shielding had varying results depending on the location of contact on the shield. No improvement was seen in the pulse noise, but the driver offset was shifted based on location contact, and multiple times the phonon channels were railed. |
| 1700 | Switch out DCRC50 for DCRCX (RevC.1 board from Soudan with IP address 131.255.52.85) to see if any difference can be discerned between the two RevC.2 boards. Flash boards and lock SQUIDs on DIB3, but run out of time to look at pulses. Leave overnight. |
| 1734 | Fill LN cold trap Dewar |