| | Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 |
| 0927 | Tower/MC/Coldplate = 33.0/30.7/188 mK, Still = 1.2 K / 0.110 mbar, G1/G2 = 260/222 mbar, 1K Pot = 1.693 K / 30 mbar, Main bath = 54.9%. Boil off rate: close to slow mode (predicted level: 56.7%). |
| 0932 | Fill LN2 cold trap bath. |
| 1230 | Start LHe transfer (MB = 50.4%) |
| 1310 | End LHe transfer (MB = 90.8%) |
| 1430 | Finish IbIs on DCRC2pC/DIB4pC/Side1pC. Previously a QET bias of -156.1 (which we've been using lately) yielded Ib*prefac of 40 uA, now it's shifted up to about 53.5 uA. Now it looks like a QET bias of -151.3 is necessary for Ib*prefac of 40 uA. |
| 1545 | Finish IbIs on DCRC2pD/DIB4pD/Side1pF. Previously a QET bias of -148.6 (which we've been using lately) yielded Ib*prefac of 40 uA, now it's nearly the same, 39.2 uA. Now it looks like a QET bias of -148.9 is necessary for Ib*prefac of 40 uA. This is in good agreement within error. |
| 1648 | Set HV = 20 V |
| 1657 | Start sequence of 12, 1-hour data series of 1-sided 20V HV data with Frontend Gain = (20/20/20)/(-/4/5), OG = 4/2, QET biases = table from Friday, with 1000 beginning randoms, no flashing, and a 15ADC bin threshold trigger on DCRC1 pA |
| | Sadly DCRC2pC/Side1pC railed briefly after this sequence began - on the 73rd event after the initial randoms. |
| 1657 | HV = 20 V, V_leak = 1 mV, V_crystal = 19.4 V |
| 1702 | Fill LN2 cold trap. (Why do I always forget to do this until after data is started?) |