Run 52

2015/04/21 through 2015/05/27 (5.3 weeks)

summary for tower meeting

The first run in the new laboratory was dedicated to testing G110, an iZIPv6 n-type crystal from Ortec, fabricated by TAMU. Critical temperatures of the TESs were measured, charge breakdown was investigated and IbIs measurements were taken. Due to issues with the DCRC boards and a interference pattern on DIB1 (Stripline 19, SQUET ZC13 and Side coax ZB1-6), data was not taken. A mixing chamber temperature of 52 mK was achieved during this run. The setup is summarized in Table 1.

A higher base temperature was seen in this run compared to the previous two runs with no tower. The tower-MC temperature difference was also higher than it should be. It appears that the main problem was a heat leak to the 100mK stage from a warmer stage. An analysis of the thermal situation is here:

Thermal Analysis of Run 52

Copied below are data tables relevant to cryogenics copied from the run diary:

The tables below briefly summarize the measured critical temperatures, normal resistances, and parasitic resistances for the phonon channels of G110. The first is sorted by DIB and the second is sorted by side.

* For DIB1 pD the IbIs curve was not extended to high enough Ib to accurately calculate the normal resistance. The value shown is an upper limit - the true value is likely smaller but it is probably greater than 2.5 Ω.

The Rn and Rp values are based on IbIs measurements. Calculation of the resistances from slopes in the raw curve depends on assumed values of the phonon circuit components and the DCRC gains. DCRC50 (Rev C.1) was used to produce all of the IbIs curves. It has been noticed in the past that when using DCRC50 the calculated Rn's are higher than when using Rev C.0 boards, suggesting that there is some incorrect assumption about how DCRC50 works. Thus the resistance values above may be higher than the true values.

Below is a map of Tc's (in mK) on the detector surfaces. There seems to be a slight tendency toward lower Tc's toward the bottom of the figure (toward DIB2) on both sides. Other trends noticed are a correlation between Tc and Rn and between Rp and Rn.

Figure 1: Tc map (in mK)

All TC Measurement test were performed with a the same DCRC board connected to the EBox - DCRC33 (rev C). A 10 mVpp / 100 Hz triangle wave was sent down the four QET lines and the phonon channels were observed as the MC was heated and then allowed to cool again. The transition region was taken as the temperature range in which the triangle waveform was distorted by pulses (below and above this range an undistorted triangle wave is observed). The lower end of the region was taken as the critical temperature, averaging the two values from warming and cooling. Temperatures were monitored at the MC thermometer; tower thermometer temperatures were inferred based on previous measurements of tower-versus-MC temperature taken over a range of base temperatures. As explained below it was determined that the temperature measured at the tower is a good indication of the crystal temperature, so the tower temperature was used to determine Tc.

The tables below are raw data copied from the run diary.

Note: DIB2 Tc's were measured twice - 2015/05/08 and 2015/05/18. For the both measurements the tower temperatures were inferred from the cooling power test done on the same day; the tower-MC temperature difference is rather smaller in the latter test. The two Tc measurements agree well when you use the corrected tower temperatures, but not so well if you use the measured MC temperatures. This suggests that the crystal is much closer to the tower thermometer temperature than the MC temperature.

The table below summarizes the minimum voltages at which charge breakdown symptoms were observed. Various polarities for sides 1 and 2 were tested. In some trials higher breakdown voltages were seen (shown in the second column) but these were not repeatable: the smaller values in the first column seem more reliable. Voltages were modified in 0.5 V steps.

The measurements in this table were performed on 2015/05/19 using DCRC31 and DCRC33 (both Rev C) and using voltage calibration tables to set true voltages rather than the nominal DCRC settings. The method was to watch pulses on DIB1 as the charge bias was adjusted. This allowed us to observe phonon pulses on Side 1 (A, B, C) and Side 2 (D), none of which are outer-ring channels. The observed breakdown symptoms were just pulse-less noise in the phonon channels, and “spiky” forms in the charge channels with no normal pulses. Also the tower temperature increases a few mK. Earlier measurements with different DCRCs and nominal voltage settings were done on 2015/05/08 and 2015/05/12 and show essentially consistent results.

This run was plagued with a high amplitude oscillation recurrently appearing in the DIB1 Qinner channel and at smaller amplitudes in the other charge channels. We refer to it as the interference problem or interference pattern for no particular reason.

Key Details:

• The pattern is ~110 kHz, strongly saturated on DIB1 Qi, around 2 Vpp on DIB1 Qo, and around 0.2 Vpp on both DIB2 Qi and Qo.
• When the problem occurs the tower temperature rises significantly.
• Turning off the power to the DIB1 FETs always gets rid of the problem.

The images below are screen caps of the interference problem as it appears in the charge traces. In this case the phonons are flatlined, which occurs when the interference appears if they are set to high gains: otherwise we typically see pulse-less noise in the phonons. The images are from DIB1/DCRC33. The traces in the other DIBs show similar behavior when the interference problem is present. Click images for large version.

Figure 1: Interference pattern in charge traces

Figure 2: Time scale zoom: frequency apparently around 110 kHz

Figure 1: Tighter time scale zoom

Diagnostics:

A similar problem was seen in Run 41 (see the figures on the Run 41 summary). In that run it appeared on DIB2 using either SQUET ZC-13 or ZC-23, but in both cases using the same side coax, ZB1-6, which was also used in this run on DIB1. So it seems that the side coax is the source of the problem.

Nader suggested that a leaky capacitor in the side coax could be responsible for the interference problem. We hooked up DIB1 and DIB2 for comparison to the breakout box and tried to check for this with the multimeter:

so no obvious problem with DIB1 in this regard.

Other Details:

• With DCRC50 (Rev C.1) the pattern would always appear immediately when the FETs were powered
• With DCRC31 and DCRC33 (both Rev C) the FETs could be powered without the pattern appearing, at least for some amount of time, depending on other circumstances
• With DCRC33 and DCRC31, the problem could be eliminated by power-cycling the FETs. The amount of time before it returned depended on other circumstances.
• With DCRC31, leaving the FETs off resulted in further heating of the tower: they had to be turned back on to cool to base again.
• With DCRC33 you could simply leave the FETs off, and the tower stayed cool
• With DCRC33 you cannot set the charge biases if the FETs are off. (this was an empirical observation: there was no effect to changing the biases, even though querying the DCRC indicated the biases were set. Turning the FETs back on resulted in observable effects indicating they was an actual bias.)
• The problem was worse (meaning it would reappear more quickly) under the following circumstances:
  • multiple DCRCs plugged in
  • non-zero charge biase applied
• The pattern can be induced by plugging something into another DIB port while the DIB1 FETs were powered.
• As far as we could tell the problem could be avoided indefinitely (and the DIB1 FETs left powered) if a Rev C board was used in DIB1, less than three DCRCs were in use, and no charge bias was applied.

Noise PSDs were produced for all twelve phonon channels with appropriate SQUID settings and QET biases. DCRC50 (Rev C.1) was used in all cases so that any differences between DIBs (e.g. due to the stripline rerouting boards, present in DIB1 and DIB2) could be assessed. Five pulse-less traces 10 ms long were used for each channel. Front End Gains were set to 50 and Output Gains were set to 8.

Color code: black=pA, red=pB, blue=pC, green=pD