UMN CDMS Wiki archive
start › cdms › k100 › run_diary › 20150519

2015/05/19 (Tuesday)

0915 MC/Tower = 52.2/66.6 mK, G1/G2 = 221/198 mbar (slow increase overnight), Still = 4 mW / 1.08 K / 0.17 mbar, 1K Pot = 1.73 K / 22 mbar, Cold plate = 9.47 kΩ / 307 mK, MC sensor = -38.61 kΩ / 69.5 mK, main bath = 32.5%
0918 Fill LN cold trap Dewar

Charge breakdown tests:

1000 DCRC31 in DIB1, DCRC33 in DIB2 as yesterday. Zap SQUIDs and set lockpoints and QET biases on DIB1. Tower base is about 74.5 mK with DCRCs powered.
Method: watch pulses on DIB1 as the charge bias is adjusted. This allows us to observe phonon pulses on Side 1 (A, B, C) and Side 2 (D), none of which are outer-ring channels. Note that tables exist relating nominal voltage settings to calibrated voltage settings: bias voltages quoted here are calibrated (true according to the table) voltages.
Interference problem: as with DCRC33 in DIB1, when the interference pattern appears the tower heats up (to 100 mK or more depending on how long it's allow to last) and the DIB1 FETs must be power cycled. What is different though with DCRC31 powering DIB1 is that the tower will continue to heat if the FETs are turned off. They must be on for the tower to cool back to normal.
1058 DIB1 0V, increase DIB2 bias in -0.5 V steps. Breakdown at 0.0 V / -5.0 V.
Breakdown symptoms: phonon channels just pulse-less noise, charge channels spiky, no normal pulses. Tower temperature increases a few mK.
Charge pulse polarity: right-side-up for -/+ biases, upside-down for +/- biases.
1058 DIB1 0V, increase DIB2 bias in +0.5 V steps. Breakdown at 0.0 V / +9.5 V.
At 4.0 V and greater on DIB2, changing the voltage causes the phonon pulses to disappear for a few seconds, as if the adjustment briefly warms them out of s/c. Phonon channels on the side being adjusted disappear for longer.
1135 Try stepping down DIB2 bias. Pulses return at 8.0 V, and repeated breakdown at 0.0 V / +8.5 V.
1156 DIB2 0V, increase DIB1 bias in -0.5 V steps. No breakdown all the way to -8.0 V. But at this point interference occurs, then breakdown.
1204 Try stepping down DIB1 bias. Pulses return at -3.5 V, and breakdown at -4.0 V / 0.0 V.
1215 Power off DCRCs and allow tower to cool for a while
1427 DIB2 0V, increase DIB1 bias in +0.5 V steps. No breakdown all the way to max possible: pulses still at +13.0 V / 0.0 V.
very frequent recurrences of the interference pattern during this run, more than twice a minute on average.
1451 Increase DIB1/DIB2 voltages symmetrically in -0.5/+0.5 V steps. Breakdown at -8.5 V / +8.5 V.
very frequent recurrences of the interference pattern again.
1511 Try stepping down biases: must decrease to -3.0/3.0 V to restore pulses. Breakdown at -4.0 V / +4.0 V.
1451 Increase DIB1/DIB2 voltages symmetrically in +0.5/-0.5 V steps. Breakdown at +5.5 V / -5.5 V.
1714 Try letting tower cool for a while then try repeating large -/+ bias, by immediately setting them from 0 rather than in steps. OK at -4.0 V / 4.0 V but breakdown at -6.0 V / 6.0 V. (Didn't try anything between them.)

Summary:

Charge breakdown minimum voltages
using DIB1=DCRC31, DIB2=DCRC33
DIB1/DIB2 polarity First breakdown seen Later minimum breakdown voltage
0/- 0.0 V / -5.5 V
0/+ 0.0 V / +9.5 V 0.0 V / +8.5 V
-/0 -8.0 V / 0.0 V -4.0 V / 0.0 V
+/0 > +13.0 V / 0.0 V
-/+ -8.5 V / +8.5 V -4.0 V / +4.0 V
+/- +5.5 V / -5.5 V

The lower values in the last two rows are close to those seen on 2015/05/12. The first two rows are not far off from those seen on 2015/05/08.

1634 Transfer LHe (final level less than 60%)
1725 Fill LN trap Dewar.