2019/04/06 (Saturday)
| Setup | DIB1/3/4 → 3.2 MHz filters 2/3/1 → cable 3/1/2 → gender changer 3/?/2 → HVConn 1/3/2 → HV 1/2 → DCRCX(4)/DCRC50(3) DCRC33(2) → 1kV power supply → HV input Lead poly shield is erected, N/E/W walls complete, no poly or lead on S wall. |
|---|---|
| 1132 | Tower = 39.2 mK |
| 1137 | We had high HV leakage return yesterday. Left it at 0V overnight. Maybe it got better? Remotely set HV=350 V using HVchange_0_to_350.msl |
| 1142 | Vleak rises slowly, then jumps from 20 mV to 110 mV at around HV = 145 V. Rises linearly from there. |
| 1149 | Sequence finishes, HV/Vleak=350 V/0.624 V |
| 1152 | Turn down HV using HVchange_350_to_0.msl |
| 1209 | Relock DCRC4 pD, but otherwise all channels look good. |
| 1212 | Start 4x background series at HV = 60→120V @ 2.42 V/min (25 min duration) with 1 minute 15% prebias CDMS detector: Driver Gains = 1x, DCRC4/3 QET biases = (440/380/430)/(500/460/410) uA, Front-End Gains = (2/2/3)/(5/2/5) 1000 BOR randoms, trigger on DCRC4pA/B/C threshold = 6/6/6 use sequence HVdrift_4x60V_2p42VPM_prebias_15_1_dur_25min.msl |
| 1216 | Vleak peaked at 31.8 mV, now around 3 mV during drifting. |
| 1246 | Fill LN2 cold trap full. |
| 1300 | Vleak did jump up to 71 mV near the end. |