2018/03/08 (Thursday)
| Status: Tried to cool to base yesterday but not successful, couldn't get the 1K Pot to work. Probably the problem is a leak from the bath to the IVC. DIB1/2 connected to DCRC50(3)/DCRC55(1). | |
| Overnight the system was left to warm to 4K and the turbopump was isolated from the IVC so we could see how much gas accumulated in the IVC overnight. | |
| 0920 | Tower = 4.3 K, 1K Pot = 4.5 K, Fridge (G1) = 544 mbar. IVC = 30 <m>\mu</m>bar - that's a lot. Main bath = 36.7%. |
| 0925 | Begin pumping out IVC with turbo pump |
| 0930 | Begin baking detector, turn on all 4 LEDs, in preparation for taking some more data. We will attempt to see the 60 keV line. |
| 1005 | Baking the detector seems to have caused a slow increase in 1K Pot and Tower temperatures. Tower/1K Pot = 4.37/5.19 K |
| 1010 | End detector bake (40 minutes) |
| 1055 | 1K Pot and Tower temperatures have flattened off since turning off LEDs Tower/1K Pot = 4.41/5.83 K |
| 1055 | Turbo = 5.4 nbar. Stop pumping IVC, we'll see how much gas we got out |
| 1220 | Interesting - the 1K Pot and Tower temperatures, which were flattish after the LEDs were turned off, started to decrease after we stopped pumping on the IVC, both settling down to 4K. This suggests that He immediately started accumulating in the IVC and acted as an exchange gas. |
| 1220 | Tower/1K Pot = 4.31/4.67 K. IVC = 460 nbar, after having it isolated for 85 minutes |
| 1250 | Start a MIDAS run and try looking at charge traces but they're all railed at 7 V. Not sure what's wrong. DCRCs are not in “stuck” mode because rd 0 in TELNET updates. Try powercycling DCRCs. |
| 1255 | First try “reset” in Telnet. Turned off MIDAS programs, did “reset”, turned MIDAS programs back on, start a run. Now one channel (DRCR3qO) is unrailed but the other 3 are still railed. |
| 1300 | Power down the DCRCs. Noticeable decrease in tower temperature when DCRCs powered off, from 4.30 to 4.25 K |
| 1310 | Tower/1K Pot = 4.25/4.58 K. IVC = 1400 nbar (still isolated from pump) |
| 1312 | Power up DCRCs, restart MIDAS programs. Again, all charge channels are railed except DCRC3qO. |
| 1320 | Try turning FET heaters on for a bit. No change. DCRC3qO does respond to changes in charge AmpOffset, but other channels don't. |
| 1323 | Apply 5V dcrc bias to all channels. See pulses on DCRC3qO. others still railed. |
| 1326 | Stop programs and power down DCRCs. |
| 1331 | Do quick electrical check on DIB2: QIbias - QObias = 9.3 nS, QObias-chassis = 15nS, QIbias-chassis = 13nS, QIFB-chassis = 6 nS, chassis-QIdrain/src=30 ns. |
| So it seems the bias side of the charge channels have some shorts to chassis now too. | |
| 1339 | DIB1 electrical check: chassis-QObias = 14 nS, chassis-QIbias = 14 nS, QI/QObias-QET D = 1 nS |
| Note: measurement increases a little over time, settles at 14.2 nS | |
| All channels show a short from bias to chassis. Only one channel was not railed: DIB3qO, which is q1, the outer channel. | |
| 1345 | Tower/1K Pot = 4.24/4.57 K. IVC = 2500 nbar (it's still isolated from pump) |
| Is the helium in the IVC somehow producing these shorts to chassis? Let's pump it out | |
| 1350 | Start pumping out IVC with turbo pump. 1K Pot temperature starts increasing a bit. A little surprising since the DCRCs are off. |
| 1425 | Tower/1K Pot = 4.30/5.57 K, both increasing. Chassis-to-DIB1qI short has not improved, 14.3 nS. |
| 1430 | Try repowering the DCRCs. Now the channels are all working! And none of them looks like it's in a high-noise state this time. |
| when the DCRCs were repowered, Tower went up from 4.3 to 4.4 K. But 1K Pot decreased from 5.63 K to 5.53 K. That's a little weird. | |
| 1435 | Two ~40kHz noise peaks are observed. In the past we saw that one is from powering each DCRC. Try turning off DCRC1 15V power (FETs). Both peaks remain, so they must not be from running the charge amplifier chain. Note that each of the two peaks is high on one or the other DCRC. i.e. each DCRC sees it's own noise strongly and the other's less so. |
| 1450 | Try applying bias to the channels. At 12V there's a definite extra wavy noise compared to 5V. It can be seen in the PSDs as raised noise in the low frequencies. From 5V to 8.5V to 12V it rose from around 6e-6 to 1e-5 to 3e-5 at 1 kHz. |
| 1450 | Set bias to 12 V on all 4 channels, then look for appropriate trigger settings. The noise doesn't look much different on the four channels, but the threshold necessary to trigger above the noise was very different among the channels (see below), don't know why. |
| 1505 | Start 1 hr series of 12V data (DCRC bias), with 1000 beginning randoms, and a 450/3500/150/100 bin threshold trigger on DIB1qI/qO/DIB2qI/qO, with 1.6384 ms pulses (8192 length) and 400 us prepulse (500 length). |
| 1520 | Fill LN2 cold trap bath. |
| 1525 | Tower/1K Pot = 4.44/5.79 K, fairly flat. |
| 1605 | Looks like dump file sizes have remained unchanged after an hour. Stop the run. Power down DCRCs. |
| 1615 | Connect switchboard with all lines except charge-related lines switched off. Connect output of Agilent 33521A function generator attenuated by 100x across QETD return line and ground. This will let us put a test signal on the bias electrode. |
| 1620 | Power up dcrcs. The function generator adds a little noise, but we are able to see the injected “pules” on the dcrc with a square wave input of 10mVpp/100=100uvPP! |
| 1626 | Start 5 min of square wave calibration data with 10Hz, 100uVpp square wave signal on bias electrode, DIB1/2 = DCRC50/55, triggering on DCRC1QI = 150 ADC bins, DCRC bias = 0V |
| 1634 | Start 5 min of square wave calibration data with 10Hz, 200uVpp square wave signal on bias electrode, DIB1/2 = DCRC50/55, triggering on DCRC1QI = 150 ADC bins, DCRC bias = 0V |
| 1640 | Start 5 min of square wave calibration data with 10Hz, 500uVpp square wave signal on bias electrode, DIB1/2 = DCRC50/55, triggering on DCRC1QI = 150 ADC bins, DCRC bias = 0V |
| 1647 | Start 5 min of square wave calibration data with 10Hz, 5mVpp square wave signal on bias electrode, DIB1/2 = DCRC50/55, triggering on DCRC1QI = 150 ADC bins, DCRC bias = 0V Bad triggering |
| 1654 | Power down DCRCs, move DCRC55 to DIB1, and put DCRC33 on DIB2. Power on DCRCs. |
| 1700 | Terrible, jagged noise seen on all charge channels. Playing with DCRC2 FET heater doesn't help. Restarting programs and/or telnet RESET doesn't help. Changing DCRC2 to master doesn't help. Power cycling doesn't help. |
| 1711 | Restart with just DCRC1 powered and enabled. Still have jagged noise. |
| 1713 | Restart with just DCRC2 powered and enabled, now it's working! |
| 1719 | Power cycle and re-seat DCRC1's Dsub plugs. Start up with both DCRCs. Now its sometimes operating correctly and sometimes going into terrible jagged noise. |
| 1725 | This is not working. Let's try different DCRCs in different places . Set up with DIB1/2 = DCRC33/50. This seems to work! |
| 1730 | Start 5 min of square wave calibration data with 10Hz, 100uVpp square wave signal on bias electrode, DIB1/2 = DCRC33/50, triggering on DCRC2QI = 120 ADC bins, DCRC bias = 0V |
| 1736 | Start 5 min of square wave calibration data with 10Hz, 200uVpp square wave signal on bias electrode, DIB1/2 = DCRC33/50, triggering on DCRC2QI = 120 ADC bins, DCRC bias = 0V |
| 1741 | Start 5 min of square wave calibration data with 10Hz, 500uVpp square wave signal on bias electrode, DIB1/2 = DCRC33/50, triggering on DCRC2QI = 120 ADC bins, DCRC bias = 0V |
| 1747 | Start 5 min of square wave calibration data with 10Hz, 5mVpp square wave signal on bias electrode, DIB1/2 = DCRC33/50, triggering on DCRC2QI = 120 ADC bins, DCRC bias = 0V |
| 1758 | Power down DCRCs and return to “standard” setup of DIB1/2 = DCRC50/55 without switchboard. |
| 1800 | Jagged noise again! Power cycle and start with just DCRC3 powered. Works fine. It seems like DCRC1 has given up the ghost! |
| 1802 | Power cycle again. Now they both work! Whatever. |
| 1805 | Set DCRC bias = 5V and choose trigger thresholds on all 4 channels. |
| 1808 | Start bias sweep data using sequence charge_bias_scan_R67.msl. This will scan through 1V → 11V and -1 V → -11 V in 2V increments, with 30s flash and 5min cooldown. 1000 beginning randoms, and a 80/80/70/70 bin threshold trigger on DCRC3QI/QO/DCRC1QI/QO = DIB1QI/QO/DIB2QI/QO |
| 1813 | Triggering on noise. Increase thresholds to DIB1QI/QO/DIB2QI/QO=100/100/90/90 |
| 1818 | Still triggering on noise. Increase thresholds to DIB1QI/QO/DIB2QI/QO=110/110/110/110 |
| 1823 | Still triggering on noise. Increase thresholds to DIB1QI/QO/DIB2QI/QO=150/150/150/150 |