| | Setup: DIB1/3/4 → SL 27/19/20 → 3.2 MHz filters → cables 2,1,3 → HV board inputs 1,3,2 → HV board outputs 1,2 → DCRC55(1)/50(3). Also DCRC4 is powered and hooked up to control the HV setting. |
| 0900 | Put 22Na source away. |
| 1100 | Tower = 22.6 mK |
| 1125 | DCRC3PC is railed again. Snap and relock it. |
| 1130 | Start Noise HV scan sequence HVscan-60_80V-15_5PreBias-30Flash-5wait-1hrData.msl Sequence takes data at 60, 70, 80 V HV biases with 15% prebias for 5 min and 30s flash with 5 min wait between each 1 hr series. Random triggering, 1000 BOR randoms. DriverGains=1, QETbias = (DCRC1PA/PB/PC)/(DCRC3PB/PC/PD) = (480/370/510)/(470/380/500). Cooldown time is short to observe baseline shifts during post-flash cooldown. |
| 1159 | HV = 59.97 V, V_leak = 2.55 mV |
| 1231 | HV = 59.98 V, V_leak = 2.30 mV |
| 1344 | HV = 69.96 V, V_leak = 2.69 mV |
| 1420 | HV = 79.96 V, V_leak = 3.35 mV |
| 1452 | HV = 79.96 V, V_leak = 3.24 mV |
| 1530 | Fill LN2 cold trap full. - It is empty, refill dewar. |
| 1530 | (Tower is cooling after flash) Tower/MC/Coldplate = 24.7/28.2/156 mK, Still = 1.5 K/0.100 mbar, G1/G2 = 264/246 mbar, 1K Pot = 1.61 K / 22 mbar (should we tweak this soon?), MB = 62.3% |
| 1646 | DCRC3PC is railed again, I doubt there's much good data for this channel. Snap and relock it. |
| 1647 | The beginning of the 20V data was compromised with the 22Na source on friday night. Retake that sequence. |
| 1648 | Start Noise HV scan sequence HVscan-0_20V-15_5PreBias-30Flash-5wait-1hrData.msl Sequence takes data at 0, 10, 20 V HV biases with 15% prebias for 5 min and 30s flash with 5 min wait between each 1 hr series. Random triggering, 1000 BOR randoms. DriverGains=1, QETbias = (DCRC1PA/PB/PC)/(DCRC3PB/PC/PD) = (480/370/510)/(470/380/500). Cooldown time is short to observe baseline shifts during post-flash cooldown. |
| 1659 | Fill LN2 cold trap full. |