UMN CDMS Wiki archive
start › cdms › k100 › run_diary › 20170717

2017/07/17 (Monday)

Previous Day

Setup: DIB 1/3/4 → 3.2 MHz filters 1/2/3 → cable 1/2/3 → gender changer 1/3/4 → DCRC55(1)/33(2)/X(4)
0855 1K pot = 16 mbar, tweak it open.
0900 Tower = 26.1 mK, Still = 0.065 mbar, G1/G2 = 174/163 mbar, 1K Pot = 1.73 K / 50 mbar. MB = 68.3%
0904 Fill LN2 cold trap full.
0950 Lab = 23.6 C, Humidity = 41%
0950 Finish IbIs on DCRC4pA/DIB4pA/Side2pE
1025 Finish IbIs on DCRC4pB/DIB4pB/Side2pF
1050 Finish IbIs on DCRC4pC/DIB4pC/Side2pD

Below are QET biases chosen for the phonon channels based on IbIs. I chose prefactors near 0.5. This avoids being too low in the transition, where TES bandwidth is reduced, but also avoids being too high, where the bias power begins to climb quickly suggesting the array is partly normal.

DIB chan Side chan QET bias Prefactor
DCRC1pA Side1pD 50.5 0.486
DCRC1pC Side1pE 58.0 0.474
DCRC2pB Side2pC -73.0 0.513
DCRC2pD Side1pC -54.5 0.445
DCRC4pA Side2pE 62.0 0.476
DCRC4pB Side2pF 68.2 0.474
DCRC4pC Side2pD 62.0 0.472
DCRC4pD Side2pB 65.0 0.484
1140 DCRC1 phonon channels are not responding to changes using the DCRC control web page. We are using the new DAQ. Tried restarting programs, didn't help. Will now try closing new DAQ and restarting old one.
  1. New DAQ is in: /home/hep/cdmssoft/repositories/SuperCDMS_DAQ_backport/scripts
  2. do ./kill_daq.sh
  3. now restart old DAQ in standard way
  4. couldn't start programs with all 3 DCRCs enabled, but could do so with only DCRC2 & 4 enabled. Maybe something wrong with DCRC1.
  5. there was a Telnet session open on DCRC1, on port 5001 - this was interfering with the new DAQ. Turning this off allowed the programs to start with all 3 DCRCs
  6. start pulse viewer, DCRC1 channels are responsive, everything OK.
1155 Now try new DAQ again
  1. shut down old DAQ
  2. relogin to cdmssoft to get rid of environment
  3. cd /home/hep/cdmssoft/repositories/SuperCDMS_DAQ_backport/scripts/ This is location of new DAQ
  4. source midas_umn.env
  5. ./start_daq.sh
  6. webpage is http://cdms2.spa.umn.edu:8082/
  7. in Programs start DCRCdriverRevC01,2,4 and readoutfe_01,2,4 and L2Trigger
  8. in VNC session, go to /home/hep/cdmssoft/repositories/SuperCDMS_DAQ_backport/scripts
  9. source midas_umn.env
  10. go to /home/hep/cdmssoft/repositories/SuperCDMS_DAQ_backport/MidasTools/GUI
  11. ./PulseViewerGUI.exe
  12. click Select/Modify Detector and Add each of T1Z1, T1Z2, T1Z4 then exit
  13. now DCRC1 is responsive.
1236 Tried starting test signal on DCRC by doing the following
  1. Going to /iZIP01/Settings/TestSignal
  2. Setting ConnectTestToQET[0] = y, DDSChipControlPin = y, DDSStartFreq = 10000, DDSDACScaling =2000
  3. No test signal.
  4. Set DDSChipControlPin = n, DDSControlReg = 3543 (0xDD7) per note here
  5. Still nothing
  6. Now DCRC1 phonons seem unresponsive to settings changes again
  7. Restart new DAQ as above
  8. DCRC1 phonon still unresponsive to changes though DCRC register values are being updated as expected
  9. Kill new DAQ and start old DAQ as above. Now DCRC1 is responsive again.
  10. Turn on test signal with: ConnectTestToQET[0]=y, DDSControlReg=3543. It works!
  11. Can adjust frequency and amplitude. Smallest amplitude that works seems to be 4.
  12. Turn off test signal with: ConnectTestToQET[0]=n, DDSControlReg=2519.
1356 Tower = 25.8 mK. Start 30 second flash. Want to see how long we need to wait after flash to cool to base. Tower peaked at 290 mK. Falls quickly to 60 mK, then cools more slowly.
1400 5 minutes after flash ended: 39 mK
1405 10 minutes after flash ended: 32 mK
1410 15 minutes after flash ended: 29 mK
1415 20 minutes after flash ended: 27.7 mK
1420 25 minutes after flash ended: 27.0 mK
1420 30 minutes after flash ended: 26.6 mK
1420 35 minutes after flash ended: 26.4 mK
1450 As on July 6 see how phonon baseline shifts with applied bias, but this time put bias on Side 2, leave Side 1 ground.
DCRC1 (Rev C.1) with x1 Driver Gains. One side biased, other side grounded.
For Side 2 bias tried negative biases as well - similar behavior but doesn't kick in until about -4 V, as opposed to +2 V.
1505 Try symmetric biasing too. It has a similar effect on phonons as one-sided biasing, such that 2.5/-2.5 is about the same as 2.5/0. Looks like the bulk field is not the important thing, it's the surface field. At any rate it looks like biases as high as 3.0/-3.0 or -3.0/3.0 have a severe effect on phonons, apparently adding significant parasitic power.
1510 With bias at -3/3 V, experimented with reducing DCRC1pC QET bias. Can get good pulses at lower bias. The falloff bias is between 51 and 52 uA; at zero bias it's 53.9 uA. So another indication of parasitic power. If we want to take biased data we'll have to redo IbIs in the biased state.
1530 Tower = 25.8 mK
1600 Tried setting bias as high as 10/-10 V, -10/10 V - saw no breakdown noise in charge traces. Phonons went flat, obviously driven to normal.
1630 Write a sequence “charge_bias_scan.msl” to take data at different symmetrical biases and flash between. Experiment with thresholds: a 100 threshold on DCRC1 q[0] seems to give some smallish phonon pulses so that will probably work.
1644 Start 15 30-minute data series of charge-bias-scan data with Frontend Gain = (15/2)/(4/4)/(5/5/5/5), OG = 4/2/4, QET biases = table above, with 1000 beginning randoms, 30 sec flash with 25 min wait, and a 100ADC bin threshold trigger on DCRC1 q[0]. Charge biases are DCRC1/2 = +/- = Side1/2 = -/+. Side 1 biases in order are 0, -0.25, -0.5, -0.75, -1, -1.5, -2, -2.5, -3, -3.5, -4, -5, -6, -8, -10
note sequence starts with a flash + 25 min wait, so first data series will begin around 1709
1710 Data has started. Tower = 27.0 mK
1710 Fill LN2 cold trap bath
1715 Quick look at data, ok so far. Only worry is that as bias increases the threshold may wind up being too low, too many triggers.

Next Day