| | Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 |
| 0850 | Tower = 33.1 mK Main Bath = 66.3% |
| 0855 | Fill LN2 cold trap bath |
| 0921 | Power cycle DCRCs 1,2. Before doing anything else, check rd 0 on both. DCRC1/2 rd 0 = changing values/0000, DCRC1/2 rd 15 = 02A0/0290, DCRC1/2 rt=00000000/00000000 |
| 0933 | Try DCRC1 wr 15 0290 to match DCRC2. But then DCRC1 rd 15=0280. DCRC1 wr 15 02A0 restores it. Weird. |
| | DCRC1 wr 15 0280 seems to take. This should disable SDRAM writing. DCRC1 rd 0 = 0000, DCRC1 rt = 00000000 Then, turn SDRAM writing on again with DCRC1 wr 15 02A0, rd 15=02A0, rd 0=updating, rt = 00000000 |
| | DCRC2 wr 15 02A0/0280 (toggle SDRAM) also toggles rd 0 updating and rd 15 changes as expected. |
| 0948 | DCRC1 wr 15 02B0/02A0 (SDRAM on, toggle external frequency reference LVDS/none)changes reg 15 as expected, but has no effect on rd 0 behavior |
| | DCRC2 rd 15=0280 (SDRAM off, no external ref), wr 15 02A0 (SDRAM on, no external ref), rd 15=02A0, wr 15 02B0 (SDRAM on, LVDS ref), rd 15=02B0. |
| | It looks like trying to change both the SDRAM enable and the frequency reference doesn't get written properly. Not sure if this is in any way related to our “hanging” output issue. |
| 1105 | One thing we haven't actually tried yet is to just restart everything: DCRCs and the entire MIDAS system. |
| 1106 | Power down DCRCs. Shut down MIDAS by using ./kill_daq_umn.sh. Using ps -u cdmssoft on cdms2 indicates there are no MIDAS programs running. Execute ./start_daq_umn.sh MIDAS web interface is up. |
| 1108 | Power DCRCs 1,2. DCRC1/2 rd 0 = updating/0000, DCRC1/2 rt = 00000000/00000000. |
| | Start MIDAS DCRC programs with DCRC2/DCRC1 = master/slave DCRC1/2. Now DCRC1/2 rd 0 = updating/updating, DCRC1/2 rt = 00000000/00000000. |
| 1114 | Start a run with random triggers. Still have DCRC1/2 rd 0 = updating/updating, DCRC1/2 rt = 00000000/00000000. |
| | Start pulse viewer. Both DCRCs show traces! It seems restarting the DAQ fixed things. |
| 1119 | Still have DCRC1/2 rd 0 = updating/updating, DCRC1/2 rt = 00000000/00000000. Which is strange, I thought rt was “read triggers” and that it would be updating once we start triggering. Though maybe its for triggers issued by the DCRC? Indeed, turning on PB threshold trigger on DCRC1 gives DCRC1/2 rt = {023B4274,023B42F4, …}/00000000 |
| 1123 | Incidentally, DCRC1/2 rd 15 = 02B0/02A1 = (SDRAM enable,LVDS reference, LVDS receiving)/(SDRAM enable,no external reference, LVDS transmit) |
| 1127 | Zap DCRC1/2 SQUIDs. |
| 1325 | Tower/MC/Coldplate = 33.2/29.7/197 mK, Still = 1.3 K / 0.110 mbar, G1/G2 = 218/200 mbar, 1K Pot = 1.665 K / 22.0 mbar. Main Bath = 59.7% (predicted level: 62.4%) |
| 1710 | Partially filled LN2 cold trap bath. Dewar ran dry, need to fill it tomorrow. |
