2017/04/28 (Friday)
| Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 | |
| PuBe source in paraffin barrel behind shield (west side) | |
| Took NaI-triggered data overnight, looks OK | |
| 0935 | Tower = 33.0 mK, Main Bath = 65.5% |
| 0935 | HV = 50.00 V, Vtest = 2.8 mV, so Vdetector = 48.8 V |
| 0945 | Trying to do IbIs on DCRC2pD, but running into similar issues as yesterday, channel seems unresponsive. This time however I'm noticing that when I set the Driver Gain to x1, that's when it becomes unresponsive - it is responsive again when I set the driver gain back to x2 or higher. Something screwy here. Notice that the registers according to Telnet (rd 4f) are not changing correctly for RevC. This behavior was seen on April 4 after we started testing DCRCX. Below is a copy of the notes from that day: |
| April 4, 16:10 | Strange behavior in DCRC2. There are pulses in pC and pD with Driver Gain =2x but when I change Driver Gain to 1x the pulses disappear, as if the QET bias has been changed. Watching the Telnet session and reading the 4f register, find that setting the DG to x1/x2/x4 changes the register to 1101/1111/1121; setting the DG to x3,x5,x6, or x7 does not change the register at all. This seems a little like Rev C.1 behavior. |
|---|---|
| April 4, 16:35 | Turn off MIDAS programs, shut down DCRCX(DCRC4), reset ODB to activate only DCRC1 and DCRC2, restart programs. Now DCRC2 seems to be working correctly. Setting DG to x1/2/3/4/7 changes the 4f register to 2111/2121/2131/2141/2171. And pulses are seen at each setting. So it seems to be working correctly now. |
| 1000 | Tried stopping programs, disabling DCRC4(X), restarting. No pulses. Tried again but this time made DCRC1 the timing link master (previously it was DCRC4). DCRC4 is disabled in ODB and unplugged from timing link, but still powered. Now it looks like DCRC2 is working correctly. |
|---|
Here's a summary of the MIDAS problems with operating DCRC2(33).
| 1055 | Finish IbIs on DCRC2/DIB4pD/Side1pF. |
|---|---|
| 1055 | Stop programs, replug timing cable from DCRC4 to DCRC1, turn programs back on. Before I did this I set all the DCRC2 Driver Gains to 2x. I checked the DCRC2 telnet session after turning the programs back on, and it looks like the registers 4f and 45 still indicate that the Driver Gains are 2x. |
| 1101 | Fill LN2 cold trap bath. |
| 1104 | Start 1 1-hour data series (#6182) of 1-sided 50V HV coincidence data with Frontend Gain = (15/15/5)/(4/3/4), OG = 4/2, QET biases = table from yesterday, with 10000 beginning randoms, no flashing, and a 22ADC bin threshold trigger on DCRC2 pD (Side1 pF). Running OR trigger of NaI detectors with PuBe source on west side of shield. NaI detector C has 311 mV threshold and detector B has 288 mV threshold |
| 1105 | Tower/MC/Coldplate = 32.8/30.5/197 mK, Still = 1.4 K / 0.110 mbar, G1/G2 = 230/215 mbar, 1K Pot = 1.696 K / 30 mbar. Main Bath = 63.3%. Boil off rate: slow mode (predicted level: 63.5%) |
| 1210 | Dial HV down to 0V |
| 1235 | Begin 1 hour bake |
| 1404 | Start This seems to be a mistake. The QET biases are not as stated - DCRC1pC is not modified as stated. It was begun at a somewhat elevated temperature, 36 mK. And the detector is still at 0V bias. |
| 1423 | Stop data sequence. |
| 1430 | Dial HV up to 65 V. After 5 minutes dial down to 50 V. |
| 1450 | HV = 50.00 V, Vtest = 2.3 mV, so Vdetector = 49.0 V |
| New standardized QET biases for HV mode based on most recent IbIs: | |||
|---|---|---|---|
| channel | QET bias | QETbias*prefactor [uA] | Date |
| DCRC1pA/DIB1pA/Side1pE | 127.6 | 30 | April 26 |
| DCRC1pB/DIB1pB/Side1pB | 139.8 | 30 | April 21 |
| DCRC1pC/DIB1pC/Side1pD | 126.4 | 30 | April 27 |
| DCRC2pB/DIB3pC/Side1pA | -117.9 | 30 | April 19 |
| DCRC2pC/DIB4pC/Side1pC | -150.4 | 30 | April 27 |
| DCRC2pD/DIB4pD/Side1pF | -147.3 | 30 | April 28 |
| 1451 | Start 1 1-hour data series (#6185) of 1-sided 50V HV coincidence data with Frontend Gain = (15/15/5)/(4/3/4), OG = 4/2, QET biases = table above, with 1000 beginning randoms, no flashing, and a 22ADC bin threshold trigger on DCRC2 pD (Side1 pF). Running OR trigger of NaI detectors with PuBe source on west side of shield. NaI detector C has 311 mV threshold and detector B has 288 mV threshold |
|---|---|
| 1609 | Start 20 1-hour data series of 1-sided 50V HV coincidence data with Frontend Gain = (20/20/5)/(3/5/2), OG = 4/2, QET biases = table above, with 1000 beginning randoms, no flashing, and a 1500ADC bin threshold trigger on DCRC4 pA (TTL signal) Running OR trigger of NaI detectors with PuBe source on west side of shield. NaI detector C has 311 mV threshold and detector B has 288 mV threshold |
| 1620 | Fill LN2 cold trap bath |