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2017/04/04 (Tuesday)

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Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33
0903 Tower/MC/Coldplate = 33.8/31.2/200 mK, Still = 1.4 K / 0.120 mbar, G1/G2 = 243/233 mbar, 1K Pot = 1.689 K / 30 mbar, Main bath = 36.8%. Boil off rate: slightly faster than slow mode (predicted level: 41.9%)
0909 Fill LN2 cold trap bath.
1040 Testing DCRCX for the first time after sending it to Sten.
1045 Unable to connect to DCRCX via telnet using its previous static IP: 192.168.96.4
1100 Connect to DCRCX via USB using procedure here. Change the following settings to what I believe they should be based on other boards and emails with Jesse :
old new
Local IP 131.225.52.181 192.168.96.4
Mac 00.80.55.ee.00.06 00.80.55.ee.05
1116 Can now connect to DCRCX with telnet using 192.168.96.4 as before.
1121 Start DCRC programs, view live traces on DCRC1, but all DCRC4 channels appear ADC railed. Changing settings does not bring any signal back. Unsure if it's electrically railed or “stuck”. rd 0 = 0000 on DCRC4 while rd 0 gives a random address on working DCRCs.
1127 Set DCRC4 wave form lengths and pre-pulse samples to be the same as other DCRCs, Power cycle DCRCX and plug in timing link. Start up DCRC programs. Now rd 0 on DCRC4 gives a random address and is showing noise traces in the pulse viewer.
1320 DCRC4 still showing traces
1520 DCRC4 still showing traces
1544 Start LHe transfer @ main bath = 26.4%
1610 Strange behavior in DCRC2. There are pulses in pC and pD with Driver Gain =2x but when I change Driver Gain to 1x the pulses disappear, as if the QET bias has been changed.
Watching the Telnet session and reading the 4f register, find that setting the DG to x1/x2/x4 changes the register to 1101/1111/1121; setting the DG to x3,x5,x6, or x7 does not change the register at all. This seems a little like Rev C.1 behavior.
1635 Turn off MIDAS programs, shut down DCRCX/DCRC4, reset ODB to activate only DCRC1 and DCRC2, restart programs. Now DCRC2 seems to be working correctly. Setting DG to x1/2/3/4/7 changes the 4f register to 2111/2121/2131/2141/2171. And pulses are seen at each setting. So it seems to be working correctly now.
1650 Stop LHe transfer @ main bath = 91.1%
1735 Finish IbIs on DCRC2pC/DIB4pC/Side1pC. At previous QETbias of -151.3 uA at which Ib*prefac was 40 uA, now it's closer to 35. The new IbIs indicates a QET bias of -152.8 uA to hit 40.
New standard QET biases from most recent IbIs measurements:
channel QET bias prefactor QETbias*prefactor
DCRC1pA/DIB1pA/Side1pE 132.7 0.301 40
DCRC1pB/DIB1pB/Side1pB 145.3 0.275 40
DCRC1pC/DIB1pC/Side1pD 130.4 0.302 40
DCRC2pC/DIB4pC/Side1pC -152.8 0.234 40
DCRC2pD/DIB4pD/Side1pF -148.9 0.269 40
1745 Set HV to 100V
1755 HV = 100.0 V, Vtest = 8.3 mV → Vdetector = 96.3 V
1757 Start sequence of 16, 1-hour data series of 1-sided 100V HV data with Frontend Gain = (20/20/20)/(-/4/4), OG = 4/2, QET biases = table above, with 1000 beginning randoms, no flashing, and a 15ADC bin threshold trigger on DCRC1 pA

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