| | Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 |
| | Overnight baking stable at 475 mK, ended at 0544 |
| 0903 | Tower/MC/Coldplate = 33.7/30.8/197 mK, Still = 1.28 K / 0.110 mbar, G1/G2 = 237/224 mbar, 1K Pot = 1.692 K / 30 mbar, Main bath = 67.7%. Boil off rate: a bit faster than slow mode. |
| 0910 | Fill LN2 cold trap bath |
| 0912 | The 0V data taken yesterday looks to have had too low of a trigger (PA=25ADC) Let's try to find a good trigger level that doesn't get too much noise. |
| 0916 | Start data series of 1-sided 0V data with Frontend Gain = table, OG = 8/4, with 1000 beginning and ending randoms, with no flashing, and a 30ADC bin threshold trigger on DCRC1 pA |
| 0930 | Cease data series. Data still looks to be more than 50% noise traces. |
| 0931 | Start data series of 1-sided 0V data with Frontend Gain = table, OG = 8/4, with 1000 beginning and ending randoms, with no flashing, and a 35ADC bin threshold trigger on DCRC1 pA. Channels rail in dump 61, event 611398 |
| 0949 | Trigger looks better now, getting ~25% noise traces. Let's let this run for an hour or two. |
| 1146 | Stop data taking. |
| 1151 | Start data series of 1-sided 0V data with Frontend Gain = table, OG = 8/4, with 1000 beginning and ending randoms, with no flashing, and a 35ADC bin threshold trigger on DCRC1 pA |
^ 1355 | Stop data taking. All channels railed. |
| 1414 | All channels except DCRC1 PC are railed, will have to look in data to see when that happened. [image not archived: doubt2.svg] |
| 1420 | DCRC2 PC/PD dominated by 400/150 kHz oscillation, lower FE gains to 4/3. |
| 1448 | Perform micro IbIs. |
| 1450 | Begin HV pre-biasing test using DCRC1 PA FE Gain/Driver Gain/QET bias = 20/8/127 |
| 1453 | Begin dialing up HV |