2017/02/21 (Tuesday)
| Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → DCRC55(1)/33(2)/50(3) (on/on/on) | |
| 0831 | Tower/MC/Coldplate = 34.0/29.8/196 mK, Still = 1.30 K / 0.110 mbar, G1/G2 = 234/220 mbar, 1K Pot = 1.678 K / 24 mbar, Main bath = 39.1%. Boil off rate: faster than slow mode. |
| 0835 | Fill LN2 cold trap bath |
| 0936 | Switch to HV mode, biasing side 2. Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 |
| In this mode, we should be able to read out all of side 1, but the only channels we're sure we are biasing are S2 A, E ,F. The others on side 2 are either half-connected (one wire-bond broken) and will thus still be biased, or they're completely open, in which case they'll float. (Or it could be that the wires and bonds are OK but there is discontinuity in the channel on the crystal.) |
| HV side 2, Readout Side 1 Map | ||
|---|---|---|
| DIB channel | Detector channel | DCRC channel |
| DIB1 PA | S1 PE | HV1 PA |
| DIB1 PB | S1 PB | HV1 PB |
| DIB1 PC | S1 PD | HV1 PC |
| DIB3 PC | S1 PA | HV2 PB |
| DIB4 PC | S1 PC | HV2 PC |
| DIB4 PD | S1 PF | HV2 PD |
| 1130 | Apply SQUID settings for each DIB channel to the appropriate DCRC in ODB. Power on DCRCs 1/2 and start MIDAS programs. |
|---|---|
| 1134 | All channels ADC railed. Connect 1kV Kepco power supply to HV board, but do not power it on. (Making this connection has caused us to need a zap in the past) Zap SQUIDs. |
| 1156 | Pulses seen on all channels except HV2 PB. HV2 PB is the “crossover” channel on the HV board. It is exhibiting more noise than other channels and does not seem to be happy with the default setting. |
| 1203 | Apply HV to detector using the 0-1 kV Kepco power supply. Increase voltage and check leakage across test resistor. At each voltage, measure leakage again after a couple minutes. Also record the baseline of the DCRC1pA trace. DCRC1 PA FE Gain/Driver Gain/QET Bias = 20/1/126.22 |
|---|
| HV [V] | Vtest [mV] | Ileak [nA] | Vcrystal [V] | DCRC1pA baseline [V] |
|---|---|---|---|---|
| 0 | 0.2 | 0.22 | -0.09 | -0.575 |
| 2 | 2.4 | 2.64 | 0.94 | -0.58 |
| 2 | 2.2 | 2.42 | 1.03 | -0.58 |
| 5 | 7.7 | 8.47 | 1.61 | -0.576 |
| 5 | 8.0 | 8.8 | 1.48 | -0.576 |
| 10 | 18 | 19.8 | 2.08 | -0.562 |
| 10 | 18.1 | 19.9 | 2.04 | -0.556 |
| 20 | 38.2 | 42.0 | 3.19 | -0.524 |
| 20 | 40.1 | 44.1 | 2.36 | -0.510 |
formulas:
- Ileak [nA] = 1.1 * Vtest [mV]
- Vcrystal [V] = HV [V] - 0.4 * Ileak [nA]
| 1229 | This leakage is considerably worse than the previous Ge HV detector, though the baseline seems somewhat stable. It is also odd that the leakage seems to increase slightly after a few minutes. We may have to try using a switchboard to shut off non-essential lines. It was later noted that base temperature rose while HV was applied, reaching 37 mK maximum before tests were ended. |
|---|---|
| 1300 | HV test with negative applied bias voltage. |
| HV [V] | Vtest [mV] | Ileak [nA] | Vcrystal [V] | DCRC1pA baseline [V] | Tower Temp (mK) |
|---|---|---|---|---|---|
| 0 | 0.1 | 0.11 | 0.044 | -0.586 | 33.7 |
| -2 | 3.4 | 3.74 | -0.50 | -0.583 | 33.8 |
| -2 | 3.3 | 3.63 | -0.55 | -0.583 | 33.8 |
| -5 | 9.2 | 10.12 | -0.95 | -0.580 | 33.9 |
| -5 | 8.6 | 9.46 | -1.22 | -0.578 | 34.0 |
| -10 | 18.7 | 20.57 | -1.77 | -0.569 | 34.3 |
| -10 | 18.9 | 20.8 | -1.68 | -0.560 | 34.8 |
| -20 | 40.5 | 44.6 | -2.18 | -0.533 | 35.9 |
| -20 | 40.5 | 44.6 | -2.18 | -0.525 | 36.4 |
| 1328 | Looking at electrical checkout sheet, it looks like DIB3 QO and DIB4 QI may have shorts to chassis. Begin modifying HV board to switch off these lines. Do this by disconnecting their HV bias resistors. |
|---|---|
| 1355 | Commence LHe transfer (29.9%). |
| 1421 | End LHe transfer (90.3%). |
| 1750 | Fill LN2 cold trap full. |