2017/02/20 (Monday)
| Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → DCRC55(1)/33(2)/50(3) (on/on/on) | |
| 0921 | Fill LN2 cold trap bath |
| 0925 | Tower/MC/Coldplate = 34.0/29.6/183 mK, Still = 1.11 K / 0.110 mbar, G1/G2 = 219/210 mbar, 1K Pot = 1.672 K / 22 mbar, Main bath = 74.2% Boil off rate: close to slow mode. |
| 1024 | Set up to take 0V data at different Prefactor*IbIs values using Matt's table. |
| QET bias settings to achieve specific dP/dI values | |||||
|---|---|---|---|---|---|
| pre*Ib: | 10 | 20 | 30 | 40 | 50 |
| DCRC1 pA / DIB1 pA | 116.56 | 117.74 | 119.4 | 122.14 | 126.22 |
| DCRC1 pB / DIB1 pB | 138.9 | 140.82 | 143.43 | 146.78 | 151.76 |
| DCRC1 pC / DIB1 pC | 123.68 | 125.29 | 127.53 | 130.93 | 137.05 |
| DCRC1 pD / DIB1 pD | 134.9 | 135.99 | 137.63 | 140.07 | 144.35 |
| DCRC2 pB / DIB3 pB | -122.01 | -123.67 | -126.2 | -129.72 | -136.35 |
| DCRC2 pC / DIB3 pC | -122.44 | -124.69 | -127.69 | -131.54 | -136.68 |
| 1034 | pre*Ib values of 20 and 40 seem too low for DCRC1 PA (fell into SC), let's start with 50 and work our way down. |
|---|---|
| 1047 | MIDAS dcrc_driver seems to not like the Driver Gain setting on DCRC2. It shows the following error message every 15 seconds or so even through DCRC2 (which has it's dirver gain set to 3) is a RevC.0 board both in reality and in the ODB. : |
<blockquote>[dcrc_driver01,ERROR] [update_phonon_functions.c:563:dcrc_driver,ERROR] ERROR: Requested value for current_phonon[2].pgagain1_2_4or_8_[3] of 3 is not allowed for RevC.1 board. Allowed values are 1,2,4,8. Keeping previous value for this Register (0x45 or 0x4f).</blockquote>
| 1050 | Setting DCRC2 Driver gains to 4 to please the beast. |
|---|---|
| 1058 | DCRC2 PB/PC not responding to QET bias changes… Try zapping DCRC2 SQUIDs. |
| 1120 | DCRC2 PB/PC still unresponsive. |
| 1130 | Play with 150mm bench testing for a little bit. Find evidence that using flexible side coax causes oscillations while vacuum coax does not. |
| 1200 | Power cycle DCRC2, re-seat detector cables. Restart MIDAS DCRC programs. |
| 1223 | DCRC2 PC seems to be responding to QET bias now, PB is railed beyond what driver offset can account for even after several re-locks. Zap DCRC2 SQUIDs. |
| 1242 | Now DCRC2 PB/PC seem to be responding again. |
| 1320 | Perform Micro-IbIs on these 6 channels. |
| 1408 | In ODB, set DCRC*/General/ChargePrepulseSamples = 500 and PhononPrepulseSamples=500. Looking at odb files from last November, I think this is what we were using. |
| 1411 | Set 70ADC bin threshold trigger on DCRC1 pA. DCRC 1 channels all seem to be in sync, but DCRC2 traces don't have pulses at any correlated time in the trace. |
| 1421 | Change the triggering channel to DCRC2 PB. It will trigger on noise up to ~500ADC bins, but above that it ceases to issue triggers? |
| 1425 | Maybe the timing link needs to be reset? Restart MIDAS programs and current MIDAS run. That seems to have fixed it. Now triggering works on either DCRC as expected. |
| All six channels on DCRCs 1&2 have the QET biases set to the pre*Ib=50 values in the table above. | |
| 1432 | Start sequence of 3 one-hour data series of 0V data with Frontend Gain = 20/6/1, OG = 8/4/1, with 1000 beginning and ending randoms, with no flashing in between series, and a 30ADC bin threshold trigger on DCRC1 pA. |
| 1457 | Terminate run early Looking at pulses in Batviewer, it's clear that DCRC1PA is dominating every event. Lower threshold to 10ADC bins. |
| 1459 | Start sequence of 3 one-hour data series of 0V data with Frontend Gain = 20/6/1, OG = 8/4/1, with 1000 beginning and ending randoms, with no flashing in between series, and a 10ADC bin threshold trigger on DCRC1 pA. |
| 1611 | Terminate run early Now it's triggering too much no noise, though DCRC1 PA pulses still look significantly larger than others. Not sure why that is, but perhaps this fooled me earlier (1457) Set DCRC1PA threshold to 20ADC bins. |
| 1614 | Start sequence of 10 one-hour data series of 0V data with Frontend Gain = 20/6/1, OG = 8/4/1, with 1000 beginning and ending randoms, with no flashing in between series, and a 20ADC bin threshold trigger on DCRC1 pA. |
| 1722 | Fill LN2 cold trap. |
| 1744 | Data seems to be triggering too much on noise. DCRC1pA has a pretty noisy baseline. So switch to trigger on DCRC1pB at threshold = 15. (This was done remotely.) |
| 1804 | Still triggering too much on noise. Increase DCRC1pB trigger threshold to 25. (Actually this was premature because there seems to be a delay in data coming in, the most recent file currently is from 17:34.) |
| 1845 | The last trigger setting seems reasonable. As noted before, DCRC1pA's pulses are much higher than the others. Since we aren't triggering on that channel it's certainly not a trigger bias. It definitely looks like pA is lower on its transition curve than the other channels. All have been set to their pre*Ib=50 values which should be high in their transitions. But as observed earlier today the values in the table clearly aren't working for DCRC1pA - apparently its IbIs curve has shifted. At least partial IbIs will need to be redone to do this properly. |
micro-IbIs results:
The plots above compare today's micro-IbIs tests to the full IbIs curves taken February 9-15. The curves are shifted based on the 300 μA point (in the case of DCRC1pA the normal curve had to be extrapolated since the IbIs was not taken out to 300 μA). None of today's measurements are consistent with the original curves - annoyingly they have all shifted. The large downward shift in DIB1pA explains why it's pulses are so much larger than the others in the current data.