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2016/11/09 (Wednesday)

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Setup: DIB1/3/4 → 3.2 MHz filters → cables 1,2,3 → HV board inputs 1,3,2 → HV board outputs 1,2 → DCRC55(1)/50(3)
HV at 0 V overnight. 88Y source is in castle behind fridge (west side).
0930 Tower/MC/Coldplate = 33.4/34.8/206 mK, Still = 1.09 K (?) / 110 μbar, G1/G2 = 175/150 mbar, 1K Pot = 1.71 K / 32 mbar. MB = 59.2%.
The two thermometers on Fridge Out 1, Still and Coldplate, seem to have transitioned to their lower-reading states
Boiloff rate: close to slow-mode
0935 Return 88Y source to safe
0950 Fill LN2 cold trap bath.
0950 Measure event rate, 46 pulses seen in 10 100-ms traces, so 46 Hz. Down from 110 Hz yesterday.
1010 bring 88Y source out to the fridge, 1 hr run till ~ 11am.
1115 Return 88Y source to safe
1400 Check phonon settings from the last 3-DCRC 2-sided data from Oct 24:
DCRC Phonon
channel
SQUID
lockpoint
SQUID
bias
QET
bias
Updated
QET
bias
1 0 -3.1 -76.5 179
1 1 -3.72 -81.2 182
1 2 -3.5 -70 184 182
1 3 -1.8 -82.6 187
2 0 1.67 50 0
2 1 2 64.9 -176 -174
2 2 3.07 60.3 -175 -173
2 3 1.5 60.6 0
3 0 -4.68 -84.8 0
3 1 -3.06 -86.7 207
3 2 -0.9 -48 165
3 3 -4.7 -51.3 202
1410 Switching from HV 1-sided to 2-sided readout mode.
1) Turn off programs TriggerFE, TowerFE, DCRCdriver. 2) Unplug power from DCRCs. 3) Unplug DCRCs and DIB cables from HV board 4) Plug DIB cables into DCRC1,2,3 5) Plug in power for DCRC1,2,3.
6) Plug in timing link cables with DCRC1 master. 7) Set ODB to enable DCRC1,2,3, disable others, set DCRC1 to Master, others to Slave. 8) Set ODB Phonon settings as table above. 9) Restart programs.
Setup: DIB1/3/4 → 3.2 MHz filters → cables → DCRC55(1)/33(2)/50(3)
1430 No channels have pulses. Some are railed, some look normal (low noise), some superconducting (high noise). Start fiddling with QET biases.
1440 All channels now show pulses. But some show the ~10kHz oscillations. Zap SQUIDs…
1520 All channels show pulses, some still have some oscillations.
1523 Take test series to make sure timing link is functioning. 20 Hz randoms, tracelength = 3.2768 ms.
1535 Remeasure background rate, 40 pulses in 1 second = 40 Hz.
1545 Reduce QET biases on three channels to reduce the 10kHz oscillations. See updated values in table above.
1550 Set Driver Gains to x8/x3/x8 on DCRC1/2/3. Adjust driver offsets to set DC offset values to around -0.8 V on all channels.
1600 Adjust trigger on DCRC3pD (Side1 pF aka TES0) so that it occasionally triggers on noise. Chose threshold = 55.
1606 Start sequence of 15 one-hour data series of 0V data with Frontend Gain = 5/2/5, OG = 8/3/8, with 1000 beginning randoms, with no flashing in between series, and a 55ADC bin threshold trigger on DCRC3 pD.
1650 Main bath = 48.2%
1655 Fill LN2 cold trap bath

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