2016/10/25 (Tuesday)

	Setup: DIB1/3/4 → 3.2 MHz filters → cables → DCRC55(1)/33(2)/50(3)
0825	Tower/MC/Coldplate = 33.6/36.1/228 mK, Still = 1.20 K / 90 μbar, G1/G2 = 120/100 mbar, 1K Pot = 1.56 K / 5.5 mbar. MB = 70.6%. Boiloff rate: slow-mode. Yesterday we forgot to let pressure out of the MB until 3 hours after the fill, but apparently that works.
0830	Fill LN2 cold trap bath.
0830	Measure event rate with Cf source present by counting pulses above noise in DIB1pA. 99 counts in 500 ms = 198 Hz
0835	Return Cf source to safe.
0845	Tweak 1K pot needle valve open a few more degrees
1130	Power off DCRCs, attach HV board, and repower DCRC1 & DCRC3 (AKA HV1 & HV2). Zap SQUIDs.
1135	Adjust SQUID and QET settings to map them to the corresponding HV channels:

HV Channel	IZIP Channel
HV1 pA	DIB1 pA
HV1 pB	DIB1 pB
HV1 pC	DIB1 pC
HV2 pB	DIB3 pC*
HV2 pC	DIB4 pC
HV2 pD	DIB4 pD
*NOTE	Phonon values flipped due to RevC → RevC.1 conversion.

1155	Turn off FETs and view channels. Adjust Driver Offsets to unrail channels.
1210	All channels unrailed, but no pulses visible. Some strange beats of noise on HV2 pB. Snap QET biases on all channels up to 600uA, then back down to see if that helps.
1225	Snapping helps HV2 pB, but attempting to change the QET bias on HV2 pD seems to have no effect (doesn't even change the baseline voltage). All other communications are being correctly transmitted from the DCRC.
	We used the table from Oct 7 to map the HV input/output. But we suspect that maybe our identification of “CONN2” and “CONN3”, two of the HV board inputs, are incorrect, and that we have the cables from DIBs 3 and 4 swapped. Actually the table was correct, and the exterior labeling on the HV box is correct (CONN1,2,3 labeled DIB1,2,3), but we didn't follow the table correctly and had them plugged in wrong.
1355	Swap Cable2 with Cable3, so Cable2 is connected to CONN3, and Cable3 is connected to CONN2. This agrees with the table. Repower DCRCs and zap SQUIDs.
	Setup: DIB1/3/4 → 3.2 MHz filters → cables 1,2,3 → HV board inputs 1,3,2 → HV board outputs 1,2 → DCRC55(1)/50(3)
1415	Adjust Driver Offsets on phonon channels and attempt to bring channels back to life.
1440	By adjusting the QET bias of HV2 pD, we are able to see pulses. So this configuration is correct. Adjust QET biases for channels that do not show pulses.
1530	Adjust all the QET biases to bring pulses back. Listed below:

1635	Turn off FETs. Set up timing link. With the Cf strong Y source out, start 5min series of 20ms length test noise data at 0V to see if the timing link is set up correctly.
1645	Stop run. Event rate is too high to get a good sense of if the timing link is working. Shorten trace length back to 3.2768ms, and raise HV1 pB's trigger threshold to 200ADC bins.
1652	Start 5min series of test noise data at 0V to see if the timing link is set up correctly.
1659	Stop run. Timing link looks like it's running well.
1710	Start 16min series of 20ms trace length noise pulses (i.e. randoms) at 0V with Frontend Gain = 5/2/5, OG = 8/3/8, no flashing.
1715	P2 at 5.5mbar. Tweak open 1K Pot needle valve 1/16th of a turn.
1725	P2 stabilizes around 24mbar. Tweak open 1K Pot needle valve another 1/16th of a turn.
1726	Stop run.
	Revert trace lengths to normal values (3.2768ms).
1730	Start 15 one-hour data series of 0V data with Frontend Gain = 5/2/5, OG = 8/3/8, with 1000 beginning and ending randoms, with no flashing in between series, and a 40ADC bin threshold trigger on DIB1 pB.
1731	Fill LN2 cold trap full.