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2016/05/11 (Wednesday)

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Setup: HV mode, DIB1/2/3 → -/Switchboard PA&PB QET bias&ret off/Open → cables → 3.2MHz Filters → HV board → HV1/HV2 → DCRC55(1)/50(3), DCRCs off overnight
Tower temperature stable overnight
0910 Tower/MC/Coldplate =46.4/43.1/282 mK, Still = 1.17 K / 0.080 mbar, G1/G2 = 115/110 mbar, 1K Pot = 1.54 K / 2.4 mbar, Main Bath = 44.9%
0915 Fill LN2 cold trap bath
1000 Taking a more careful look at DIB3's leakage. Leakage measured immediately after bias change and again ~2-5min later, when it seems to have reached a stable value.
Bias [V] Leakage [mV] Tower Temp (mK)
DIB3 with diverter board connected. All others floating.
0 0 46.3
4.995 7→1.6 46.6
10.00 10.6→3.0 46.6
15.00 11.6→8.7 47.1
20.01 17.0→16.1 47.7
25.00 26.3→24.9 49.0
0 -3.6 46.5
1115 We're suspecting a path to ground in one of the QET bias/ret lines, specifically DIB2 PA. Measure this resistance directly by connecting cable to breakout box and using multimeter to test QET lines to chassis.
Cable unplugged from ebox
Any QET→chassis 0.07 nS 14 GΩ
Raw Conductance Corrected Resistance (=raw-0.07nS)
DIB 1 QET→chassis
PA 0.14 nS 14.3 GΩ
PB 0.13 nS 16.7 GΩ
PC 0.13 nS 16.7 GΩ
PD 0.11 nS 25.0 GΩ
DIB 2 QET→chassis
PA 0.70 nS 1.6 GΩ
PB 0.18 nS 9.1 GΩ
PC 0.16 nS 11.1 GΩ
PD 0.17 nS 10.0 GΩ
DIB 3 QET→chassis
PA 0.17 nS 10.0 GΩ
PB 0.14 nS 14.3 GΩ
PC 0.13 nS 16.7 GΩ
PD 0.12 nS 20.0 GΩ
1340 Tower/MC/Coldplate = 46.2/43.1/268 mK
1350 Bang fridge from from west. CP spikes to 278 over 30 seconds then falls to 255 mK after 3 minutes.
1355 Tower/MC = 45.3/42.6 mK. So banging the fridge may have helped slightly
1415 Tower/MC = 43.9/40.8 mK. Then stays flat for the next hour.
1600 Measure some resistances between phonon channels (QET bias pins) using FLUKE 87V multimeter in nS scale:
DIB1 DIB2 DIB3
pA pB pC pD pA pB pC pD pA pB pC pD
DIB1 pA
DIB1 pB 1.1 [a]
DIB1 pC 0.13 0.14
DIB1 pD 0.11 0.12 0.16
DIB2 pA 0.18 0.05
DIB2 pB 0.26 40 [b]
DIB2 pC 0.11 0.1
DIB2 pD 0.13 0.1 0.12
DIB3 pA 0.16 10 [c] 0.11
DIB3 pB 0.16
DIB3 pC 0.08 0.14 24 [d]
DIB3 pD 0.16 0.06 0.15 0.13 0.14
[a] Starts higher, then drifts down after a minute. Inner and central Side1 channels
[b] Temperature spikes to 50 mK. Outer and central Side2 channels
[c] Temperature spikes to 46 mK. Adjacent central Side2 channels (different DIBs)
[d] Temperature spikes to 47 mK. Inner and central Side2 channels
  • So it seems there are some low resistance paths between some adjacent channels, but not between every adjacent pair.
  • No opposite-side pairs have low resistance paths
  • Low resistance paths are not limited to same-DIB channels
1800 Fill LN2 cold trap full.

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