2016/05/10 (Tuesday)
| Setup: HV mode, DIB1/2/3 → -/Switchboard PA&PB QET bias&ret off/Open → cables → 3.2MHz Filters → HV board → HV1/HV2 → DCRC55(1)/50(3), DCRCs on overnight | |
| Tower temperature stable overnight | |
| 0907 | Tower/MC/Coldplate =48.0/45.0/290 mK, Still = 1.13 K / 0.080 mbar, G1/G2 = 112/111 mbar, 1K Pot = 1.19 K / 2.0 mbar, Main Bath = 75.6% |
| 0910 | Fill LN2 cold trap bath |
| 1050 | Plug in only DIB2 to the EBox and repower DCRCs. Before zapping SQUIDs we see pulses on HV2 pD, and some strangely triggered pulses on HV2 pC. Zap SQUIDs. |
| 1055 | After zapping SQUIDs, all channels railed, but not at ±1.25 like normal. Currently HV2 pC & pD are railed at -0.08V. Relocking does nothing. Attempt to change Driver Offset and see if that helps. |
| 1100 | Changing Driver Offset has no effect. Zap SQUIDs, since that's what got us into this. |
| 1110 | Still railed at these weird values. Unpower DCRCs. |
| 1130 | Disable DCRC1 in ODB. Repower DCRC3, and look at pulses. HV2 pC & pD are railed at expected values. Adjusting Driver Offset brings them to showing pulses. Zap SQUIDs to see if we can reproduce the issue. |
| 1145 | After unrailing the two channels by adjusting Driver Offset, HV2 pC & pD still showing pulses. Looks like the power cycling did the trick. No to apply bias. |
| 1200 | Tested first 150mm LED board. Using LED test mode of multimeter. They seem to have survived the soldering process, huzzah! |
|---|
| Off | UV on | IR on |
|---|---|---|
 |  |  |
| 1205 | Applying HV bias to crystal produced the following results: |
|---|
| HV (V) | Leakage (mV) | Baseline pC (V) | Baseline pD (V) |
|---|---|---|---|
| 0.001 | 0.1 | -0.435 | -0.638 |
| 5.002 | 3.6 → 1.3 | -.315 | -0.518 |
| 7.51 | 2.9 → 1.2 | 0.051 | -0.131 |
| Note: | At 7.51V the pulses disappeared on both phonon channels. After ~10 minutes at this voltage, minor bumps could be seen on HV2 pD, though no pulses actually broke through the white noise. |
||
| 1230 | Lower HV back to 0, and unpower DCRC3. |
|---|---|
| 1357 | Only DIB 2 connected, no switchboard. Looking more closely at heating. |
| HV (V) | Leakage (mV) | MC (mK) | Tower (mK) |
|---|---|---|---|
| 0.001 | 0.1 | 45.3 | 46.8 |
| 5.000 | 7 → 1.6 | 45.4 | 46.5 |
| 10.01 | 12 → 11.5 | 45.2 | 46.3 |
| 15.01 | 24 → 27 | 45.1 | 46.6 |
| 20.00 | 38 → 38 | 45.2 | 46.5 |
| 25.00 | 49 | 45.2 | 46.7 |
| 30.00 | 56 → 58 | 45.1 | 46.7 |
| 35.01 | 63 | 45.3 | 46.7 |
| 40.01 | 75 | 45.3 | 46.6 |
| Now it seems we can't get DIB2 to cause heating… We saw heating the other day when everything was left floating except DIB2 PB QET bias/ret. Let's try to repeat that. | |
| Only DIB2 connected with switchboard, all lines off except PB QET bias/ret. |
| HV (V) | Leakage (mV) | MC (mK) | Tower (mK) |
|---|---|---|---|
| -0.004 | 0.0 | 43.5 | 46.7 |
| 5.01 | 7→1.6 | 43.6 | 46.9 |
| 10.01 | 10→5.3 | 43.4 | 46.7 |
| 15.01 | 11→5.2 | 43.6 | 46.8 |
| 20.00 | 14→12→15 | 43.5 | 47.7 |
| 25.00 | 24→25.6 | 43.8 | 49.6 |
| 30.01 | 35.6→37→34 | 44.2 | 50.9→51.1→50.3* |
| 35.03 | 43.4→45 | 44.3 | 52.1→51.7* |
| 30.00 | 33.0→33.8 | 44.3 | 50.8* |
| 0.009 | -19 | 44.0 | 47.0 |
| 35.02 | 60→43.6 | 44.0 | 51.5* |
*Unstable +/- 0.5mK
| So it seems we can cause heating by biasing a single set of QET bias/return lines, but allowing other channels to be connected as well increases leakage, but without heating. | |
| 1700 | Fill LN2 cold trap full. |