| | Setup: iZIP mode, DIB1/2/3 → cables → 3.2 MHz filters → DCRC55/33/50 |
| | Taking Y-Be data overnight, last flash ~ 07:00 |
| 0900 | Remove strong Y source from fridge |
| 0905 | Tower/MC(H35)/MC sensor/Cold Plate = 31.7/28.0/43/170 mK, Still = 1.34 K / 0.090 mbar, G1/G2 = 125/105 mbar, 1K Pot = 1.53 K / 2.8 mbar, Main bath = 72.7% |
| 0905 | Tweak 1K Pot needle valve open additional 5 degrees. |
| 0910 | Fill LN2 cold trap Dewar. |
| 1127 | Check phonon traces. All look good. |
| 1130 | Start test background series with standard setup at 0/0 V with FG=5/2/5, OG=3, with 1000 initial randoms, 0 ending randoms, no flash. Trigger on DIB1 phA with threshold of 20ADC bins and DIB1 qInner&qOuter each with threshold 210 ADC bins, with 150 us pileup cut window. Stop after initial randoms are done. |
| 1200 | Unpower DCRC55, detach PiFilter connector, and attach Pi Filter switch board. Switch on filters for all phonon channels, so that the only channels not filtered are pins: 42, 26, 11, 27, 12, 30, 15, 31, 16, 50, 45, 46, 49. |
| | Power on board and zap SQUIDs. |
| 1215 | Check phonon pulses, 3 on DIB1 are railed and one on DIB3. Adjust Driver Offsets. All good. |
| 1220 | Start test background series with pi-filter switch board with all phonon lines filtered at 0/0 V with FG=5/2/5, OG=3, with 1000 initial randoms, 0 ending randoms, no flash. Trigger on DIB1 phA with threshold of 20ADC bins and DIB1 qInner&qOuter each with threshold 210 ADC bins, with 150 us pileup cut window. Stop after initial randoms are done. |
| 1230 | Realize that I forgot to put the copper shield on the pi-filter switch board… So let's redo that one. |
| 1242 | Start test background series with shielded pi-filter switch board with all phonon lines filtered at 0/0 V with FG=5/2/5, OG=3, with 1000 initial randoms, 0 ending randoms, no flash. Trigger on DIB1 phA with threshold of 20ADC bins and DIB1 qInner&qOuter each with threshold 210 ADC bins, with 150 us pileup cut window. Stop after initial randoms are done. |
| 1505 | 1K Pot has fallen to 4.5 mbar, tweak needle valve open additional 5 degrees again |
| 1510 | Turn on filters for all charge-related pins on pi-filter switch board. Now the only unfiltered lines are 26, 42, 45, 46, and 49, the LED and FET heater and FET Tsense lines. Attach board to DIB1 with shields. |
| 1515 | Power up the DIB1 DCRC, establish timing link, zap SQUIDS |
| | Hitting the ZAP button on DCRC Control seemed to start and finish the sequence correctly according to the progress window, but there was no change in base temperature or still pressure, so I don't think it worked. |
| 1540 | The MIDAS frontends weren't started, which caused the zapping malfunction. Once started, zapping works fine. |
| | Pulses look fine. One DIB2 channel was railed, but changing the Driver Offset fixed it. |
| 1542 | Start test background series with shielded pi-filter switch board with all phonon and charge-related lines filtered at 0/0 V with FG=5/2/5, OG=3, with 1000 initial randoms, 0 ending randoms, no flash. Trigger on DIB1 phA with threshold of 20ADC bins and DIB1 qInner&qOuter each with threshold 210 ADC bins, with 150 us pileup cut window. Stop after initial randoms are done. |
| 1600 | Unpower DCRC55, remove shielded pi-filter switch board. Attach pi-filter connector, and repower board. Zap SQUIDs. All but one channel looks good. Adjust Driver Offset of railed channel, and it looks just fine. |
| 1733 | Fill LN2 cold trap full. |
| 1735 | P2 at 8.5mbar, open 1K pot needle valve a little bit more. |
| 1753 | Start 14 hours of 30min Y-Be series at -4/+4 V with FG=5/2/5, OG=3, with 1000 initial randoms, 1000 ending randoms, with 30s flash and 25 minute cooldown in between series. Trigger on DIB1 phA with threshold of 20ADC bins and DIB1 qInner&qOuter each with threshold 210 ADC bins, with 150 us pileup cut window. |
| 1755 | Place Strong Y source in Be disc sourceholder. |