2015/09/17 (Thursday)
| Current setup: iZIP mode, DIB1/2/3 → cables → 3.2 MHz filters → → DCRC55/33/50. | |
| Overnight: taking Cf data last night. Spikes in tower temperature last night until about 2:40. This is after data taking had completely stopped. Largest spike at 22:18 up to 33.2 mK. | |
| 0920 | Fill LN cold trap Dewar |
| 0925 | Tower/MC(H35)/MC sensor/Cold Plate = 31.0/25.3/45.5/158 mK, Still = 1.32 K / 0.085 mbar, G1/G2 = 175 mbar, 1K Pot = 1.72 K / 22 mbar, Main bath = 48.7% |
| 0935 | All phonon channels still look good. |
| 1020 | Remove Cf source from behind shield and place in safe. Bring Ba source out to place inside of shield just below the top. |
| Test event rate from Ba source (Count pulses in 5 100ms traces and multiply by 2). |
- No source: 28Hz
- At top of shield: 80Hz (32% pile up)
- Opposite side of fridge, 3“ above top of shield: 66Hz (26% pile up) (we have a winner)
| 1024 | Temperature begins to rise for unknown reason. No obvious noise on phonon channels other than increased event rate. Temperature spikes up to 32mK, but drops back down to 31.2mK (instead of 31.0mK). |
|---|---|
| Shelving observed on DIB3 pulses. Unpower DCRC50 and wait to see if temperature drops back to base. | |
| 1053 | Notice that the temperature has stayed impossibly flat for the past few minutes. The resistance bridge connection seems to be loose and firming up the connection causes the temperature to re-read at 30.5mK. Repower DCRC50. |
| 1110 | Pulses back, but still mild shelving on DIB3pC. |
| Temperature sudden spike to 45.5mK. Not sure why. | |
| 1112 | Temp back down to 31mK. |
| 1113 | DIB2pD railed (maybe related to temp spike). Relock brings it back. |
| 1130 | Temperature still erratic. Oscillating between 30.7 and 31.4mK. Overnight it oscillated between 30.8 and 31.1mK. |
| 1135 | Start data regardless with thresholds increased by 10 like yesterday, and all the same settings. (-/+2V then -/+4V.) |
| 1145 | About 2 minutes into triggered data, the event rate bogged down to ~1Hz. Delete old data series from Vuk-01. Increase all phonon thresholds by another 10 ADC bins. |
| 1150 | Start Ba data again. This time event rate = ~13Hz. |
| 1200 | Pumped out the LHe transfer tube vacuum jacket - the tube felt cold during yesterday's transfer. Pumped down to 1.4e-2 mbar (pumping pressure). |
| 1305 | Put Ba source back in safe. |
| 1310 | Start MIDAS tests. |
| 1340 | Prepare for background data. Set phonon thresholds back to original values. |
| A | B | C | D | |
|---|---|---|---|---|
| DIB1 | 40 | 35 | 45 | 45 |
| DIB2 | 30 | 60 | 25 | 30 |
| DIB3 | 45 | 45 | 45 | 45 |
| When checking pulses, notice that many are railed. Checking the DCRC settings, it's because the MIDAS settings are using old values for Driver Offsets. Revert to the new settings. | |
| 1343 | Notice that ~10min ago, the temperature rose first to 45mK, dropped a bit then rose to 52mK, dropped to 39mK then rose again to 49mK. |
| 1353 | Looking at registers 45 & 4F on DCRC50, they read B181 and 8181, respectively. This means Zap Enable is turned on for all phonon channels on DIB3. Set 0101 to turn off Zap Enable bits and any other gains applied. |
| Check other boards, but Zap Enable bit wasn't enabled. Set 0101 for good measure. Temperature begins to fall slowly. | |
| 1407 | Had to change several Driver Offsets on DIB3 to prevent channels from railing. Set them manually, because I get the feeling they'll change back eventually. |
| 1417 | Tower temperature at 31.5mK. Prepare to take data without DAQDAQ, so new files don't need to be made for the new Driver Offsets. Start 15 minute background data series at -/+2V. |
| 1435 | Stop data series. Flash for 30s. |
| 1455 | Set -/+4V and start 15 minute background data series. |
| 1515 | The rate got bogged down at some point during the run. Though file sizes suggest that we got over 3/4 of the way through. Stop run and flash. |
| Give DAQ over to MIDAS for tests. | |
| 1636 | MIDAS tests stopped. Get DAQ set up properly. Several channels railed. |
| 1640 | Cf source placed at top of shield. |
| 1644 | Fill LN2 cold trap full. |
| 1655 | Set DAQDAQ to take 4 cycles of -/+2V and -/+4V Cf data with the usual settings. |
| Phonon thresholds set to 65 ADC bins across the board. |