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2015/09/09 (Wednesday)

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Current setup: iZIP mode, DIB1/2/3 → cables → 3.2 MHz filters → DCRC55/33/50.
Overnight data taking with flashing between. Last flash at 23:00 last night
0950 Pulses still look OK except DIB1 pB has an unexplained 80 Hz pattern.

This is the same DCRC channel as the 80 Hz pattern seen in HV mode yesterday. DCRC55pB apparently is sometimes getting a test signal or something.

0955 Fill LN2 cold trap full.
1000 Tower/MC(H35)/MC sensor/Cold Plate = 31.1/26.8/41.2/157 mK, Still = 1.37 K / 0.085 mbar, G1/G2 = 145 mbar, 1K Pot = 1.74 K / 22 mbar, Main bath = 31.8%.
1010 Power cycle DCRC55 to get rid of 80Hz pattern
1040 When applying yesterday's settings, DIB1 phonon channels railed. Relock brings back pC, but the others require setting the Frontend Gains to 1 in order to bring them back. After this, FG could be set back to 16/5 without the channels railing.
Create new MultiDAQ files to do Frontend Gain sweeps of 16/5/16, 10/3/10, 5/2/5, 1/1/1 (in that order on DIBs 1/2/3).
1155 Take front-end gain sweep noise data: Start DAQDAQ2 to take 1000 initial randoms at the 4 different Frontend Gain values (Output Gain=3). In order to do this, Run Time had to be set to 2 minutes to properly take all the randoms. Because of this, there was ~30s of triggered data after each Random series.
1420 Begin LHe transfer at main bath = 25.7%
1505 Cease LHe transfer (94.8%).
1625 After some MIDAS tests, DCRCs were stuck in some kind of constant-zapping mode (Registers 45&4f on DCRC33 displayed 8181 when read instead of 3131 like the RevC.1 boards). This state led to a tower temperature of ~70mK, but the Still seemed to be more dramatically heated: P1 rose to 0.28mbar, G1/G2: 300/280mbar.
1650 Writing 3131 to registers 45&4f on DCRC33 decreased the temperature gradually to ~60mK, but then the temperature plateaued. Power cycle boards and allow fridge to cool.
Again, when applying saved settings, phonon channels rail, but changing Frontend Gain to 1 brings the channels back, and they can then be reset to 16 or 5.
1720 Seeing the 80Hz pattern on DIB1 pB from earlier. Power cycle DCRC55.
1745 Prep DAQDAQ2 for overnight Cf run.
  • 1000 initial randoms
  • 2000 events/file
  • 15 minute series, 30s flash, 30 minute cooldown
  • OR trigger across all phonon channels (no trigger on pB1 because of noise seen at 1835)
  • 4 cycles, each cycle consisting of first a -/+2V then a -/+4V series
1815 Put Cf source in shield near detector for overnight Cf run.
Measure event rate for different Cf source placement by looking at 500ms of data and counting peaks:
Source Placement Event Rate Pile Up %
No Source 34Hz 14%
Top of Shield 56Hz 22%
Down 3“ 78Hz 31%
Choose Top of Shield for source placement.
1820 Fill LN2 cold trap full.
1830 Set phonon settings to below values, which allow for a reasonable DAQ rate (~11Hz):
Phonon thresholds
pA pB pC pD
DIB1 50 50 50 55
DIB2 45 50 45 60
DIB3 60 80 50 55
1835 Seeing 80Hz pattern again on DIB1 pB. Don't want to take time to power cycle board, so change trigger settings to not trigger on pB1.
1845 Take neutron data: Start DAQDAQ2 for overnight run.

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