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2015/09/08 (Tuesday)

	Current setup: DIB1/2/3 → cables → 3.2 MHz filters → HV1/2 → DCRC50/55. Unused LED is grounded.
	Overweekend, Cf source in shield activating detector
0930	Fill LN2 cold trap full.
0935	Tower/MC(H35)/MC sensor/Cold Plate = 30.8/25.9/40.0/151 mK, Still = 1.38 K / 0.075 mbar, G1/G2 = 145 mbar, 1K Pot = 1.74 K / 24 mbar, Main bath = 68.5%.
	Remove Cf-252 source from fridge.
0945	Mini-bake detector (4 LEDs - two from each DCRC).
1000	Notice that FETs are off on HV2. Power them up.
	Realize that HV bias was still applied during mini-bake. Turn HV bias to 0V and mini-bake again.
1035	At 0V HV bias, set up phonon thresholds.

Phonon thresholds
	pA	pB	pC	pD
HV1	45	35	75	-
HV2	-	45	45	25

1040	Still seeing ~80Hz noise on HV2pB with amplitude of twice white noise. (This seems to be a DCRC55pB problem, see tomorrow's diary entry)
	Apply 0V HV bias to crystal (leakage current of 1.5nA). Start 10 minute data series.
1057	Stop Data. Flash 30s.
1115	Apply +5V to crystal (leakage current of 7.3nA). No noticeable shift in phonon baselines. Start 10 minute data series.
1129	Stop data. Zero HV bias. Flash 30s.
1151	Apply +10V to crystal (leakage current of ~15.4nA). Start 10 minute data series.
1205	Stop data. Zero HV bias. Flash 30s.
1220	At ~12V, HV2pB starts showing upside down pulses, and HV2pC needed a relock.
	Set HV=11.5V and allow signals to “settle.”
	Adjust driver offsets to place baselines at ~-0.7V.
1225	Upside down pulses still on HV2pB, but other HV2 pulses are essentially gone (breakdown). HV1 still showing good pulses.
	Apply +11.5V to crystal (leakage current of 16.1nA). Start 10 minute data series.
1239	Stop data. Zero HV bias. Flash 30s.
1245	Disconnect HV Box and DCRCs.
1255	Set up iZIP mode, DCRC55=DIB1, DCRC33=DIB2, DCRC50=DIB3 in the configuration: EBox → Cable → Gender Swap → 3.2MHz Filter → DCRC
	Power DCRCs, zap SQUIDs.
1330	Several channels railed and noise looks larger and spikier than usual. Check cable connections.
1550	Stop DCRC50 and power cycle to see if noise goes away.
1612	No more spiky noise on DIB3. Set up channels with FG=16/5/16 (for DIBs 1/2/3), OG=3. Adjust Driver Offsets to place phonon baselines at ~-0.7V Set phonon thresholds below:

Phonon thresholds
	pA	pB	pC	pD
DIB1	50	50	50	55
DIB2	45	50	45	60
DIB3	55	65	50	55

1650	Create 0V MultiDAQ file from above settings. Create -/+2V file as well.
1715	Set DAQDAQ to take 8 cycles of 15 minute data series with 30s flash and 30 minute cooldown in between series. 1000 initial randoms. 2000 events/file. OR trigger across all phonon channels. Start data series. No phonon baselines shifted or railed.
1720	Fill LN2 cold trap full.