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2015/09/03 (Thursday)

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Current setup: DIB1/2/3 → cables → 3.2 MHz filters → HV1/2 → DCRC50/55. Currently the unused LED on the HV board has been grounded - previously it just floated
Overnight, Cf source in shield activating detector, detector baking with two LEDs available through HV board
0935 Remove Cf-252 source from fridge. Fill LN2 cold trap full.
0940 Tower temperature at 183 mK. Stop baking detector, and temperature begins to drop.
1008 Tower cools to 32 mK after 28 minutes
1035 Tower/MC(H35)/MC sensor/Cold Plate = 30.9/24.7/40.4/152 mK, Still = 1.33 K / 0.080 mbar, G1/G2 = 155 mbar, 1K Pot = 1.72 K / 22 mbar, Main bath = 63.1%.
italicized temperatures from Fridge Out 1 cable are still elevated for some reason
Main bath boiloff rates have been relatively high since Aug 28. About 1.8%/hour when the bath is at 50%, normal seems to be closer to 1.6%
1050 ~180Hz sine wave in most phonon channels. Temperature elevated. Also see spike pattern in charge channels.
1053 Power cycle DCRCs.
1105 Apply SQUID and QET settings. Noise still present on phonon channels. Unpower DCRCs and wait for fridge to cool all the way to base this time.
Temperature excursions after turning off the DCRCs

The first drop is right after powering down. The later excursions are not unusual occurrences after powering down the DCRCs after a “bad state”.

1230 Temperature has dropped below 31mK and it's relatively stable in its decline.
1245 Change to Mixing Chamber. More stable at 24.2mK.
1252 Tower temperature more stable now: 30.5±.25mK. Power up DCRCs.
1320 Pulses are back and the only noise we see is the usual 5mVpp ~150Hz.
1324 Never mind, the bad state is back, but it went away after ~30s, though. This brief bad state wasn't accompanied by any temperature rise.
1327 Bad state is back. ~20mVpp on HV1 and ~30mVpp on HV2.
1330 Noise gradually decreases to nothing.
1500 Applying HV with smaller supply. Monitor HV1pA baseline:
HV board with all three DIBs, filters
HV (V) Ileak (nA) Baseline Elevation (mV)
5.00 8.8 0
10.0 17.7 0
15.0 26.1 0
15.7 26.6 0
16.0 27.0 +30
16.2 27.5 +40
16.5 28.0 +100
16.9 28.6 +190
17.4 29.6 +270 (phonon pulses disappearing)
17.7 30.3 +270 (phonon pulses dead)
slope is 1.71 nA/V (0.587 GΩ)
Phonon baseline rises then comes back down after measuring Ileak. 180Hz sine wave comes and goes.
1515 Bring HV to 0. Spiky noise back on charge channels. Power cycle DCRCs. Unplug DIB2 DIB3.
1520 Repower DCRCs
1535 Set up DCRC50 (HV1), see 60Hz sine wave on Qi, Qo, but not on phonon channels. ~10mVpp.
1545 Realize that I unplugged DIB3 when I meant to unplug DIB2. Power off DCRCs, plug in DIB3. Unplug DIB2. This will mean that both Side 2 charge channels and 2/6 Side 2 phonon channels won't be biased (including Side2pA, the outer channel)
1610 After loading all of the settings, HV1 channels look good. HV2pB is only HV2 channel that should show pulses, but it's just railed.
1615 All of a sudden, 50KHz, 150mVpp noise seen on HV2pB. 20mVpp noise also on HV1Qi and Qo.
1616 Apply HV, monitor HV1pA baseline:
HV board with DIBs 1 and 3 only, filters
HV(V) Ileak (nA) Baseline Elevation (mV)
5.00 5.9 0
6.00 5.3 0
7.0 6.5 +215
7.5 7.1 +275, phonon pulses disappear
15 22.0 +275 (Tower Temp 30.8 → 31.7mK)
-5.00 -8.2 0
-6.00 -8.6 0
-7.0 -9.4 +200
-7.5 -9.0 +280 (phonon pulses gone)
slope is 1.28 nA/V (0.779 GΩ)
1648 Unpower DCRCs. Unplug DIB3. Only DIB1 plugged in. This means only one phonon channel biased on Side 2, all other phonon and charge channels floating.
1647 Power up HV1 (DCRC50). Before zapping, notice ~60Hz 100mVpp sine wave in Qi, Qo. Power cycle.
1659 Noise still there. By touching shield of cables to top of fridge and bottom of EBox, noise disappears.
1708 Apply HV, monitor HV1pA baseline:
HV board with DIB 1 only, filters
HV(V) Ileak(nA) Baseline(mV)
5.0 3.5 65
6.0 3.5 65
8.0 5.9 65
9.5 4.0 340 (pulses gone)
8.0 3.6 (drifts upward) 72 (measuring Ileak drops it back to 65mV)
9.0 3.9 68
9.5 3.3 340 (pulses gone)
slope is 0.486 nA/V (2.06 GΩ)

If we calculate Vcrystal as Vbias - Ileak * 0.43 GΩ, we find that for 3 DIBs and 2 DIBs pulses disappear at around Vcrystal = 4.5 V, as before, but in the 1 DIB case we seem to be able to bias it to 7.3 V.

1726 Unpower DCRC50. Plug in DIBs 2&3. Repower DCRCs.
1743 Boards all set up. Bake overnight.
1750 Fill LN2 cold trap full.

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