2015/06/25 (Thursday)

Previously used gains, with DCRC31/33/50 → DIB1/2/3 :

frontend/true output
	DIB1	DIB2	DIB3
pA	7/1	7/1	7/2
pB	4/1	4/1	7/2
pC	7/1	7/1	7/1
pD	7/1	7/1	7/1

Now using DCRC55 → DIB1

0816	Stop flashing detector
0851	Fill LN cold trap Dewar
0853	MC/Tower/Cold plate = 25.3/31.3/142 mK, Still = 2 mW / 1.10 K / 0.11 mbar, G1/G2 = 205/190 mbar, 1K Pot = 1.68 K / 15 mbar
0915	Set all DCRC 55 DIB1 phonon gains to 7/“1” (2 is actual gain).
0924	Adjust DIB2 driver offsets: 0.086/ 0.044/ -0.016/ 0.028
0925	Adjust DIB1 driver offsets: -0.018/ -0.014/ -0.006/ -0.024
0950	Flash for ~5 sec. w/ all 3 DIBs.
0955	Remove Cf source. Place Ba source at 6“ down from top of shield.
1010	Apply -4.0 V to both Qi and Qo on DIB1 and then calibrated +4 V to Qi/Qo on DIB2; on DIB3, D looks like it's got upside down pulses.
1015	Commence taking Ba data.
1031	Stop data, zero Q bias, flash.

At times 1040 - 1241, phonon thresholds of 50.

1040	Set charge biases to -/+ 4 and start data.
1050	Fill LN cold trap full.
1058	Stop data, zero charge, flash.
1111	Start Ba data series.
1129	Stop data run, zero Q bias, flash.
1140	Start Ba data series.
1158	Stop data run, zero Q bias, flash.
1208	Start Ba data series.
1230	Stop data, zero charge bias, flash.
1241	Start Ba data series.
1300	Stop data run, zero Q bias, flash.; change thresholds to 25 ADC bins.
1320	Allison enters clean room for roughly 5 minutes to look at source holders. Opens purge cabinet on the right.
1322	Had to manually change trigger threshold for DCRC 50 through PUTTY.
1323	Start Ba data run.
1340	Stop data run, zero Q bias.
1353	Flash.
1407	Start Ba data run.
1540	Stop data run, zero Q bias, flash.
1545	Remove Ba source. Commence taking background data.
1605	Start bkg data run.
1622	Stop data run, zero Q bias, flash.
1642	Start bkg data run.
1700	Stop data run, zero Q bias. Zap Squids on DIB3 in hopes of fixing D3 which has weird dips in the pulses.
1711	All channels on DIB3 look “good” now, but D came back at an increased baseline (i.e., +0.4 V instead of -0.8 V). Change D3 driver offset from 0.028 V to -0.156 V. Had to relock C1 and D1. Change C1's driver offset from -0.016 V to 0.032 V.
1720	Save Multi-DAQ configuration in preparation to test DAQDAQ.
1731	Begin data run w/ DAQDAQ2; 3 data series of -/+4 V (10 min. each); only C1 shows a shifted baseline at ~ -0.4 V.
1802	During second series, A2 is railed at +1.2 V. Stop data run. Change A2 driver offset from 0.086 V to 0.032 V to unrail it.
1807	Flash w/ all 3 DIBs.

Calculated optimal QET biases for DCRC55→DIB1 using IbIs curves, R = Rnormal/4:

DCRC55→DIB1 QET biases
pA	72 μA
pB	101 μA
pC	79 μA
pD	73 μA

1757	Fill LN2 cold trap full.

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