2020/08/02 (Sunday)
- Lab in-person: Matt
- Virtual partner: Zach, Michael
| Setup | Run 73. DIB 1/3/4 → Stripline 43/48/41 → pi-filters 1/2/3 → Cable 3/1/2 → nothing/nothing/accessory_interposer → HV_Conn 1/3/2 → HV 1/2 → DCRCX(4)/DCRC55(1)-master; DCRC33(2) → HV control. DCRCs on overnight. Lead/poly shield erected (4 lead walls, 2 poly walls). |
|---|---|
| 0920 | MB = 34.5% |
| 1015 | Tower = 49.7 mK |
| 1110 | Check phonon channels with pulse viewer. All are fine but the oscillations in DCRC4pC look stronger, possible because the temperature is lower. I think DCRC1pD oscillations are stronger too. It's triggering too much. |
| 1125 | Decrease QET bias on DCRC1pD, 440→420 uA, and on DCRC4pC, 390→370 uA, to decrease oscillations. We'll want to do a new IbIs at the now lower temperature |
| 1140 | Write a sequence for 10V drifted data, similar to the last 5V one - multiple loops, 10-second steps, same drift rate as before. HVdrift_10V_22p3mVps_multiloop10_nopre_60min.msl |
| 1146 | Start a 60 min series at HV = 10V, drifting 0.0223 V/s, no prebias, CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (0,320,370,0)/(0,360,420,420) uA, Front-End Gains = (3/3/3)/(5/5/5) 1000 BOR randoms, trigger on DCRC1pD threshold = 8 Use sequence HVdrift_10V_22p3mVps_multiloop10_nopre_60min.msl |
| 1146 | Tower = 49.7 mK |
| 1147 | Vtest = 0.5 mV, shortly after drift begins |
| 1156 | Vtest = 0.9 mV. HV = 21.1 V. Charge/Bias = 11.0112. Lag ratio ~ 1.13 |
| 1252 | Vtest = 3.1 mV, HV = 89.4 V. Drift ends. Overall lag ratio = 66/60 = 1.10. |
| Luke gain was pretty flat for the first 29 minutes of this series, then fell off. Drift rate seems to have been nice and constant though. | |
| 1555 | Matt Fritts body temperature 97.4 F |
| 1620 | Matt enters lab |
| 1625 | Tower/MC/Coldplate = 49.9/30.2/193 mK, Still = 1.51 K / 0.18 mbar / 5 mW, G1/G2= 368/335 mbar, 1K Pot = 1.64 K / 24±2 mbar. |
| 1649 | Begin LHe transfer @ MB = 20.8% |
| 1655 | Switch HV leads so HV is set for negative bias. HP leads are oriented with the detector leads, so HP will display negative bias. |
| 1710 | Fill LN2 cold trap bath |
| 1725 | End LHe transfer @ MB = 91.9% |
| 1745 | MB = 90.6% |
| After the fridge computer rebooted, the Arduino browser tab https://create.arduino.cc/editor/flyingfeet213/083dfa23-4f45-4eaa-87c7-e62b2ff1883e no longer allowed a connection to the Arduino board. Turns out you need to double-click “Arduino_Create_Bridge - Shortcut” on the desktop, then communication will work. |
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| 1805 | Matt leaves lab |
| 1840 | Start a 60 min series at HV = -10V, drifting -0.0223 V/s, no prebias, CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (0,320,370,0)/(0,360,420,420) uA, Front-End Gains = (3/3/3)/(5/5/5) 1000 BOR randoms, trigger on DCRC1pD threshold = 8 Use sequence HVdrift_10V_22p3mVps_multiloop10_nopre_60min.msl |
| 1840 | Tower = 52.5 mK, still cooling since it rose during/after the transfer |
| 1842 | Vtest = -0.6 mV, shortly after drift begins. |
| 1946 | Vtest = -4.0 mV, HV = -89.7 V, drift ends. Lag ratio = 66/60 = 1.10, good. |
| 1946 | Tower = 52.0 mK |
- For this first -10V drifted data, the Luke gain fell linearly for about 35 minutes, then flattened out for the rest. Let's repeat this, see if the pattern is the same.
| 2145 | Start a 60 min series at HV = -10V, drifting -0.0223 V/s, no prebias, CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (0,320,370,0)/(0,360,420,420) uA, Front-End Gains = (3/3/3)/(5/5/5) 1000 BOR randoms, trigger on DCRC1pD threshold = 8 Use sequence HVdrift_10V_22p3mVps_multiloop10_nopre_60min.msl |
|---|---|
| 2145 | Tower = 52.3 mK |
| 2147 | Vtest = -0.6 mV, shortly after drift begins. |
| 2251 | Vtest = -3.8 mV, HV = -89.3 V, drift ends. Lag ratio = 66/60 = 1.10, good. |
| 2251 | Tower = 52.0 mK |
- This second -10V drifted series shows the same pattern as the first. Interesting.
- Let's first assume that the applied HV is actually rising at a constant rate (the LabVIEW readouts definitely appeared that way but we can investigate more closely)
- update: I checked, it looks good.
- Note that there is a level gain period in both the positive (at the beginning) and the negative (at the end) - so in those periods the counter bias rises at the same rate as the applied bias
- But for negative bias, the counter bias grows more quickly at the beginning. For positive, it grows more quickly at the end.
- To make the negative bias gain flat at the beginning, should change nominal drift rate from 22.3 to 23.9 mV/s.