UMN CDMS Wiki archive
start › cdms › k100 › run_diary › 20191107

2019/11/07 (Thursday)

Previous Day

Setup DIB1/2/4 → 3.2 MHz filters → cable 1/2/3 → gender changer 1/2/3 → movable source controller/board with external Feedback resistor/nothing → DCRC55(1)/DCRC33(2)/DCRC50(3)
Baked last night and took some data series. But Tower temperature is elevated, settled to 59 mK after bake, slowly cooled to around 58 mK this morning. Seems like the DCRCs are in a bad state.
0835 Tower/MC/Coldplate = 58.3/34.4/195 mK, Still = 1.51 K/ 0.150 mbar / 0 mW, G1/G2= 78/64 mbar, 1K Pot = 1.74 K / 150±20 mbar. MB= 25.9%
0840 Take a look at the channels - seeing pulses in all phonon channels. See traces in charge channels (no pulses cuz I left the bias off). So nothing looks bad.
Turn off DAQ programs, I'll power down DCRCs one by one.
Unplugging DCRC50(3) causes an initial temperature spike then a precipitous drop. Looks like that one was causing the heating.
0855 Tower = 44.2 mK and continues to fall.
0855 Fill LN2 cold trap bath
0920 Tower/MC/Coldplate = 42.7/34.4/185 mK, with DCRCs off. Still cooling.
0920 Power on DCRCs and turn on DAQ programs again. First, on ODB turn off 15V Power on DCRC3, shouldn't need it. Tower spikes to 46 mK then cools again.
0935 Tower settled to 43.5 mK but it is slowly rising, now 44.0 mK
0940 Adjust 1K Pot needle valve. Accidentally opened it about 5 degrees - now closing it a little. Originally was at about 40 degrees, now about 30.
0955 1K Pot settles at 1.71 K / 68±3 mbar
1205 Tower = 44.3 mK, slowly falling.
1215 Begin LHe transfer @ MB = 18.9%
1245 End LHe transfer @ MB = 92.3%
1305 Tower = 43.9 mK
1310 1K Pot = 1.68 K / 42±2 mbar. It settled downward after the LHe transfer.
1315 Zap all SQUIDs. Again the tool in the DCRC Control UI doesn't work, so run the sequence testzap.msl instead.
1330 Tower = 44.4 mK, settling after the zap.
1345 Apply +4/-4 bias (to qI&qO on DCRC1/2)
1350 Start 60 min Bkg data series with S1/S2 = +/-4 V with previous phonon settings, Driver gain = 1, with 1000 initial randoms,
trigger on DCRC2pA/B/C/D = 8/8/8/8 ADC
using sequence timed_run.msl
note: triggering from just one DCRC to avoid multitriggering
DCRC1pC railed a few minutes in. Later DCRC1pD railed as well. Not a very good dataset.
1440 End data series a little early
1500 Adjust the Front-end Gain on DCRCpC and pD down a little, cuz they had some ugly noise. This seems to help.
1505 Adjust DCRC1pD QET bias from 100.8 to 105, because it looked like it was falling into superconducting.
1510 Turn charge biases to 0V, then flash detector for 30 seconds
1605 Tower = 43.4 mK
1605 Apply +4/-4 bias (to qI&qO on DCRC1/2)
1608 Start 60 min Bkg data series with S1/S2 = +/-4 V with edited phonon settings, Driver gain = 1, with 1000 initial randoms,
trigger on DCRC2pA/B/C/D = 8/8/8/8 ADC
using sequence timed_run.msl
1655 Tower = 43.3 mK.
1655 Fill LN2 cold trap bath
1710 Ground and flash detector for 30s.
2320 Tower = 42.6 mK
2325 Start Bkg Bias scan at S1/S2 = 0,+/-4,+/-8,+/-12 V, Driver gain = 1, with 1000 initial randoms, 30 min data, 30s flash with 30 min cooldown
trigger on DCRC2pA/B/C/D = 8/8/8/8 ADC
using sequence qbias_scan_r71_pm_0_4_8_12.msl

Next Day