2019/07/18 (Thursday)
| Setup | DIB1/3/4 → 3.2 MHz filters 2/3/1 → cable 3/1/2 → gender changer ?/3/2 → HVConn 1/3/2 → HV 1/2 → DCRCX(4)/DCRC55(1) DCRC33(2) → 1kV power supply → HV input Three walls of the lead/poly shield are up. |
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| Status: Cooling down after a fridge failure. Tower temperature flat overnight between 79.8 and 79.9 mK. Looks kinda stuck there. |
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| 0840 | Fill LN2 cold trap bath. |
| 0900 | Tower/MC/Coldplate = 79.8/63.6/333 mK, Still = 3.9 K / 0.26 mbar / 0 mW, G1/G2 = 133.1/148.1 mbar, 1K Pot = 1.72 K / 90 mbar. MB = 66.6% |
| Comparisons to before the failure: Tower of course is high. So is everything else - MC high as well, so probably can't blame it on slow cooling of the Tower components. Coldplate and Still are very high (Still temperature doesn't even make sense). I guess this could be a helium film on the upper components, thermally shorting them to warmer parts… maybe affects the Still thermometer more than the Still itself? | |
| Guess we can try heating the still again, see what happens. | |
| 0925 | Turn the Still heater on to 6 mW Still 0.26→0.32 mbar. Circulation pressures rise a bit. Tower temperature rises slightly |
| Let's leave it like this for a bit, then maybe experiment with the 1K Pot, which is running warmer than before the failure. | |
| 0940 | Tower = 81.3 mK and is slowly rising. Still heating is not helping. |
| 0940 | Turn off still heater. |
| 1115 | Tower is back to it's previous 79.9 mK |
| 1115 | Look at traces. All railed. Zap SQUIDs. Now we see noise traces. Tower temperature falling! Looks like the DCRCs were elevating the temperature. We're even seeing pulses now :) |
| 1150 | Tower = 40.5 mK :) |
| 1150 | Experimenting with trigger. Messing with baseline&sample widths, threshold, and driver gain. In the process we seem to have knocked DCRC1 into a constant-triggering mode. Power cycle DCRCs and zap SQUIDs. |
| Note: when we turned the DCRCs back on and turned on the DAQ programs, we had the problem we've had before that DCRC2 got set to version 3.1 instead of 3 in the ODB, which means it turned the HV up to 500V. We had to stop the programs, set the ODB back to 3, then start again, and the voltage went back to 0. | |
| 1245 | Found some pretty good trigger settings for DCRC1pD (Side1pF): Baseline/Sample length 120/28, threshold 6, with DriverGain still at 1. |
| 1255 | Check event rate. Count number of visible pulses in 50 traces, three trials: count 12, 6, 16 pulses. 69±12 Hz. Calmed down a lot since last checked 2 days ago, several hours after the overnight activation. |
| 1259 | Start a sequence of 8 @ 50 min series at HV = 180→306V, rate 2.49V/min, with 10% prebias for 2 minutes, flash at end with 30 min wait. CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (490/400/495)/(420/480/450) uA, Front-End Gains = (2/2/3)/(5/5/5) 1000 BOR, 5Hz InRun randoms, trigger on DCRC1pD threshold = 6, baseline/sample length = 120/28 (standard 16/5), phonon pre-pulse 500 (standard is 500). Use sequence HVdrift_8X180V_2p49VPM_loopversion_prebias_10_2_dur_50min_flashDCRC_1_4.msl |
| 1300 | Tower/MC/Coldplate = 38.9/30.2/198 mK, Still = 1.29 K / 0.10 mbar / 0 mW, G1/G2 = 102/110 mbar, 1K Pot = 1.71 K / 80 mbar. |
| DCRC4pB railed at the beginning of the second series, 07190718_1453. | |
| 1525 | Adjust DCRC4pB driver offset to unrail it. It's fixed by Minute 33 of series 07190718_1453. |
| 1530 | Fill LN2 cold trap bath. |
| 1559 | Chad (IT) unplugged a DCRC's ethernet cable by mistake when we were fooling around with an arduino. This crashed dcrc driver. I think this was after data finished, but before the flash. |
| 1614 | Stop sequence, HV=0. Manually flash detector. |
| 1648 | Start a sequence of 8 @ 50 min series at HV = 180→306V, rate 2.49V/min, with 10% prebias for 2 minutes, flash at end with 30 min wait. CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (490/400/495)/(420/480/450) uA, Front-End Gains = (2/2/3)/(5/5/5) 1000 BOR, 5Hz InRun randoms, trigger on DCRC1pD threshold = 6, baseline/sample length = 120/28 (standard 16/5), phonon pre-pulse 500 (standard is 500). Use sequence HVdrift_8X180V_2p49VPM_loopversion_prebias_10_2_dur_50min_flashDCRC_1_4.msl |
| 2326 | PC has been railed for a while. During a post-flash cooldown, adjust the driver offset to bring it back. |
| 2327 | Stop sequence. PC was railed for most of them. Last flash occurred around 2320. Let's wait till 2350 and restart the sequence to get a full set of 8 series. |
| 2350 | Start a sequence of 8 @ 50 min series at HV = 180→306V, rate 2.49V/min, with 10% prebias for 2 minutes, flash at end with 30 min wait. CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (490/400/495)/(420/480/450) uA, Front-End Gains = (2/2/3)/(5/5/5) 1000 BOR, 5Hz InRun randoms, trigger on DCRC1pD threshold = 6, baseline/sample length = 120/28 (standard 16/5), phonon pre-pulse 500 (standard is 500). Use sequence HVdrift_8X180V_2p49VPM_loopversion_prebias_10_2_dur_50min_flashDCRC_1_4.msl |
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| There could be some M-shell here… |
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