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2019/06/13 (Thursday)

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Setup DIB1/3/4 → 3.2 MHz filters 2/3/1 → cable 3/1/2 → gender changer ?/3/2 → HVConn 1/3/2 → HV 1/2 → DCRCX(4)/DCRC55(1)
DCRC33(2) → 1kV power supply → HV input

Three walls of the lead/poly shield are up.
0715 Start a 74 min series at HV = 220→400V, rate 2.418V/min with 10% prebias for 2 minutes, flash at end with 30 min wait.
CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (490/400/490)/(420/480/450) uA, Front-End Gains = (2/2/3)/(5/5/5)
1000 BOR and 1000 EOR randoms, trigger on DCRC1pB/C/D threshold = 6/6/6.
Use sequence HVdrift_220V_cal0612_2p418VPM_prebias_10_2_dur_74min_flashDCRC_1_4.msl
  • Noise widths based on PTOF (unbalanced) for +180V, +200V, +220V → 400V data in the last couple days:
    • 180V: 20.6 eVee
    • 200V: 24.2 eVee
    • 220V: 26.6 eVee
0905 Fill LN2 Cold trap bath
0915 Tower/MC/Coldplate = 42.1/32.8/201 mK, Still = 1.29 K / 0.090 mbar, G1/G2 = 148/136 mbar, 1K Pot = 1.64 K / 24 mbar. MB = 67.7%
italicized values were taken while the tower was still cooling after a flash.
1054 Start a 99 min series at HV = 160→400V, rate 2.418V/min with 10% prebias for 2 minutes, flash at end with 30 min wait.
CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (490/400/490)/(420/480/450) uA, Front-End Gains = (2/2/3)/(5/5/5)
1000 BOR and 1000 EOR randoms, trigger on DCRC1pB/C/D threshold = 6/6/6.
Use sequence HVdrift_160V_cal0612_2p418VPM_prebias_10_2_dur_99min_flashDCRC_1_4.msl
1402 Start a 100 min series at HV = 140→400V, rate 2.418V/min with 10% prebias for 2 minutes, flash at end with 30 min wait.
CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (490/400/490)/(420/480/450) uA, Front-End Gains = (2/2/3)/(5/5/5)
1000 BOR and 1000 EOR randoms, trigger on DCRC1pB/C/D threshold = 6/6/6.
Use sequence HVdrift_140V_cal0612_2p418VPM_prebias_10_2_dur_100min_flashDCRC_1_4.msl
  • Noise width based on PTOF (unbalanced):
    • 160V: 22.9 eVee
    • 140V: 25.1 eVee
1645 Fill LN2 Cold trap bath
1650 HV is meant to be set at 0, but is reading 2.2 V. Why is that calibration drifting now?
Adjust the low end of the calibration file HV_calibrations/HV_DCRC2_control_cals_440V_190612.txt
1711 Start a 30 min series at 0V
CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (490/400/490)/(420/480/450) uA, Front-End Gains = (2/2/3)/(5/5/5)
1000 BOR and 1000 EOR randoms, trigger on DCRC1pB/C/D threshold = 6/6/6.

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