2019/06/04 (Tuesday)
| Setup | DIB1/3/4 → 3.2 MHz filters 2/3/1 → cable 3/1/2 → gender changer ?/3/2 → HVConn 1/3/2 → HV 1/2 → DCRCX(4)/DCRC50(3) DCRC33(2) → 1kV power supply → HV input |
|---|---|
| 0000 | Tower = 47.9 mK |
| 0925 | Tower/MC/Coldplate = 47.4/31.1/178 mK, Still = 1.02 K / 0.095 mbar, G1/G2 = 181/176 mbar, 1K Pot = 1.63 K / 22 mbar. MB = 35.0% coldplate and still are reading in their “low” modes for whatever reason |
| Tower temperature continues to fall linearly, slowly | |
| 0930 | Fill LN2 Cold trap bath |
| Let's investigate HV again. Yesterday's HV test suggested we had almost zero current leakage (Vtest<0.1 mV from 0 to 440V). But then when we did the data run we had significant leakage (Vtest = 50 mV at HV = 300→400V). | |
| 1132 | Over ~10 min, turn HV up to 325 V. Leakage current increases, then falls slowly with each bias increase. Stopped at HV/Vtest = 326 V / 44 mV, consistent with the data run yesterday and with past runs. Maybe the Keithley 617 was in a different mode before the data run yesterday? Matt said he did bump it yesterday and set it to the correct mode before the data run. |
| 1135 | As HV is turned down to 0 V, tower temperature starts to increase?! At some point while dialing down HV, the leakage current briefly spiked to 300 mV. This was followed by significant increase in tower temperature (47.4→47.9 mK - doesn't sound big but it's noticeable) and also a small shift in Still pressure, 0.095→0.100 mbar. |
| 1140 | DCRC4 channels are all ok but DCRC3 channels are all railed. Tower temperature is not cooling back to its previous base so maybe we're in a “bad state”… Can't unrail the DCRC3 channels. In “Open” polarity I see the trace, but relocking back to “Non-inverted” doesn't work, even if QET bias = 0. |
| 1145 | Turn off DAQ programs than power down DCRC3. After a couple minutes Tower temperature and Still pressure go back down. |
| 1245 | Power DCRC3 on again and restart programs. Same problem - all channels railed, and temperature rising again. Can see a trace in pC but only if the driver offset is set all the way to 2, and no pulses. Turn off programs and power down DCRC3 again. |
| 1325 | Also power down DCRC4, just in case that's necessary to get out of the bad state. |
| 1345 | Power DCRC4 again, tower rises 0.5 mK before falling again. Power DCRC3. No immediate heating. |
| 1350 | Start DCRC programs, tower temp starts to rise. As before, DCRC3 channels railed but can see noise on PC with high driver offset. |
| 1352 | Turn off DCRC3 QET biases. Tower = 47.8 mK and rising. Turn off SQUID biases too. Tower = 47.9 mK and rising. |
| 1400 | Toggle DCRC3 15V power on then off again. Tower continues to heat. Stop DCRC programs and power down DCRC3. Tower starts cooling. |
| 1430 | Swap out DCRC3 with DCRC1. Apply appropriate SQUID and QET settings to DCRC1. |
| 1443 | Power on DCRC1. Tower=47.2 mK and cooling. \\Start DCRC programs. Tower rises to 47.7 mK, then starts cooling again. |
| 1457 | Tower = 47.2 mK, can see all 3 channels on DCRC1. PB is showing pulses, the other 2 are just noise with the default settings copied from DCRC3. |
| 1510 | Snapping DCRC1 channels and returning to the default QET values gives us pulses. Zap DCRC1,4 SQUIDs. |
| 1525 | Start LHe transfer @ MB = 26.2% |
| 1608 | End LHe transfer @ MB = 94.3% |
| 1640 | Good pulses on all channels. |
| 1645 | Use the python code to generate a sequence to drift the bias from 300 to 400 V at 3.9 V/min, now with DCRCs 1 and 4: |
python HVscan.py -iDCRC 2 -HVs 300 -HVcalFile HV_calibrations/HV_DCRC2_control_cals_440V_190603.txt -HVdriftRate 0.065 -HVpreBias 5/1 -tSeries 25 -DCRCs2Flash 1,4 > ../../sequencer/HVdrift_300V_3p9VPM_prebias_5_1_dur_25min_flashDCRC_1_4.msl
| 1648 | Start a 25 min series at HV = 300→400V, rate +3.9V/min with 5% prebias for 1 minute, flash at end with 30 min wait. CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (420/370/440)/(420/400/450) uA, Front-End Gains = (2/2/3)/(5/5/5) 1000 BOR and 1000 EOR randoms, , trigger on DCRC1pA/B/C threshold = 6/6/6. Use sequence HVdrift_300V_3p9VPM_prebias_5_1_dur_25min_flashDCRC_1_4.msl |
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| 1657 | Fill LN2 cold trap full. |
| 1701 | Data is started. Pulses are okay, but there is some nasty looking breakdown noise too. HV/Vleak = 305V / 59.5 mV |