2017/12/26 (Tuesday)
| Setup: DIB1/3/4 → SL 27/19/20 → 3.2 MHz filters → cables 2,1,3 → HV board inputs 1,3,2 → HV board outputs 1,2 → DCRC55(1)/50(3). DCRC4 → HV power supply. | |
| 1920 | Tower/MC/Coldplate = 21.6/25.5/147 mK, Still = 1.2 K / 0.100 mbar, G1/G2 = 214/177 mbar, 1K Pot = 1.63 K / 28 mbar, MB = 60.5% |
| circulation pressures, Coldplate, and maybe Still temp all unusually low | |
| 1925 | Fill LN2 cold trap bath |
| 1925 | Reverse HV bias polarity. We'll try some data at negative HV |
| 1930 | Start sequence of 12 30-minute background data series at HV = -70V, Driver Gains = 2x, QET biases = 480/360/440/480/380/490 uA, Front-End Gains = 10/5 on DCRC1/3, 1000 initial randoms, trigger on DCRC1pA threshold = 8, flashing then waiting 30min after each series, using modified triggerfe, using sequencer script DataLoop_70V_30min_groundflash_30min |
| 1941 | The first data sequence has started HV = -69.75 V, V_leak = -3.50 V. That's a bit higher leakage at this polarity, at least at this early point after the prebias. |
| 1945 | Phonon baselines look OK. |
| 1955 | HV = -69.75 V, V_leak = -3.29 V. |