| | Setup: DIB1/3/4 → SL 27/19/20 → 3.2 MHz filters → cables 2,1,3 → HV board inputs 1,3,2 → HV board outputs 1,2 → DCRC55(1)/50(3). DCRC4 → HV power supply. |
| 1755 | Tower = 21.7 mK |
| 1757 | Begin LHe transfer @ MB = 25.9% |
| 1805 | Fill LN2 cold trap bath |
| 1852 | End LHe transfer @ MB = 91.5% |
| | Another long sequence like a yesterday |
| 1900 | Start sequence of 12 30-minute background data series at HV = 70V, Driver Gains = 2x, QET biases = 480/360/440/480/380/490 uA, Front-End Gains = 10/5 on DCRC1/3, 1000 initial randoms, trigger on DCRC1pA threshold = 8, flashing then waiting 30min after each series, using modified triggerfe, using sequencer script DataLoop_70V_30min_groundflash_30min |