| | Setup: DIB1/3/4 → SL 27/19/20 → 3.2 MHz filters → cables 2,1,3 → HV board inputs 1,3,2 → HV board outputs 1,2 → DCRC55(1)/50(3). DCRC4 → HV power supply. |
| 0735 | Tower = 21.8 mK |
| 0735 | HV = 69.89 V, V_leak = 2.45 mV |
| 1720 | Tower/MC/Coldplate = 21.7/25.4/155 mK, Still = 1.3 K / 0.100 mbar, G1/G2 = 224/201 mbar, 1K Pot = 1.62 K / 26 mbar, MB = 19.9% |
| 1730 | Begin LHe transfer @ MB = 19.9% |
| 1735 | Fill LN2 cold trap bath |
| 1828 | Finish LHe transfer @ MB = 91.9% |
| | We'll do another long sequence like a yesterday, but try a lower trigger thresshold |
| 1852 | Start sequence of 12 30-minute background data series at HV = 70V, Driver Gains = 2x, QET biases = 480/360/440/480/380/490 uA, Front-End Gains = 10/5 on DCRC1/3, 1000 initial randoms, trigger on DCRC3pC threshold = 11, flashing then waiting 30min after each series, using modified triggerfe, using sequencer script DataLoop_70V_30min_groundflash_30min |
| | First series: 1904 |
| 1910 | HV = 69.90 V, V_leak = 2.78 mV |
| 1910 | Tower = 21.6 |