| | Setup: DIB1/3/4 → SL 27/19/20 → 3.2 MHz filters → cables 2,1,3 → HV board inputs 1,3,2 → HV board outputs 1,2 → DCRC55(1)/50(3). DCRC4 → HV power supply. PuBe source present. |
| 0915 | Tower/MC/Coldplate = 21.7/24.2/152 mK, Still = 1.3 K / 0.100 mbar, G1/G2 = 250/220 mbar, 1K Pot = 1.62 K / 24 mbar, MB = 66.7% |
| 0920 | Fill LN2 cold trap bath |
| 1030 | Dial HV up to 70 V with 15% 5-minute prebias, using changeHV_0_70_preBias15_5.msl |
| 1040 | HV = 69.94 V, V_leak = 3.23 mV |
| 1040 | Adjust driver offset on DCRC3pB. Other channels look good. |
| 1040 | Modify QET bias on DCRC1pC down from 450 uA to 440 uA. Intent is to avoid being driven into oscillations during pulses. |
| 1045 | Estimate event rate from random traces. Set PhononWaveformLength on DCRC1 to 131072 which is 52.4288 ms and counted visible pulses in 27 pA traces. Counted 104 pulses in 4.4156 seconds, so event rate is around 73.5 ± 7 Hz. |
| 1055 | Since DCRC3pD(Side1pF) has oscillations, it's not great for triggering - we've been getting trigger bursts after a muon. So experiment with DCRC1pB(Side1pB) triggering. Threshold around 10 seems good, seems to just dip into noise. |
| 1105 | Remove PuBe source from lab and move it to storage container in PAN 443 |
| 1117 | Start 14-minute background data series at HV = 70V, Driver Gains = 2x, QET biases = 480/360/440/480/380/490 uA, Front-End Gains = 10/5 on DCRC1/3, 1000 initial randoms, trigger on DCRC1pB (Side1pB) threshold = 10 |
| | aborted early to de-rail DCRC3pB |
| 1120 | HV = 69.90 V, V_leak = 2.80 mV |
| 1126 | DCRC3pB is railed. Try adjusting its Driver Offset. |
| 1130 | DCRC3pB is still railed. We'll stop this run and start over. |
| 1131 | Stop data series. Then adjust DCRC3pB driver offset. |
| 1133 | Start 2-minute background data series at HV = 70V, Driver Gains = 2x, QET biases = 480/360/440/480/380/490 uA, Front-End Gains = 10/5 on DCRC1/3, 1000 initial randoms, trigger on DCRC1pB (Side1pB) threshold = 10 |
| | aborted early because we should remeasure the background rate |
| 1135 | Stop data series |
| 1135 | Estimate event rate from random traces. Set PhononWaveformLength on DCRC1 to 131072 which is 52.4288 ms and counted visible pulses in 66 pA traces. Counted 102 pulses in 3.4603 seconds, so event rate is around 29.5 ± 3 Hz. |
| 1143 | Start 97-minute background data series at HV = 70V, Driver Gains = 2x, QET biases = 480/360/440/480/380/490 uA, Front-End Gains = 10/5 on DCRC1/3, 1000 initial randoms, trigger on DCRC1pB (Side1pB) threshold = 10 |
| | DCRC3pB railed during 16th dump. Bastard. |
| 1145 | HV = 69.90 V, V_leak = 2.71 mV |
| 1148 | Trigger threshold seems to low. Adjust from 10 up to 12. |
| 1320 | Stop data series. |
| 1330 | Adjust Driver Offset on DCRC3pB |
| 1334 | Start 34-minute background data series at HV = 70V, Driver Gains = 2x, QET biases = 480/360/440/480/380/490 uA, Front-End Gains = 10/5 on DCRC1/3, 1000 initial randoms, trigger on DCRC1pB (Side1pB) threshold = 12 |
| | DCRC3pB railed after like 2 minutes |
| 1408 | Stop data series |
| 1410 | Start 60-minute background data series at HV = 70V, Driver Gains = 2x, QET biases = 480/360/440/480/380/490 uA, Front-End Gains = 10/5 on DCRC1/3, 1000 initial randoms, trigger on DCRC1pB (Side1pB) threshold = 12 |
| 1432 | Adjust DCRC3pB Driver Offset. It's not railed but it has crept upwards. |
| 1439 | Remove Pfeiffer gauge from turbo pump. Disassemble and clean elements, then reassemble and put back on turbo pump. |
| 1432 | Adjust DCRC3pB Driver Offset again. It's still not railed but it was very high so hitting ADC saturation sooner. |
| 1454 | Adjust DCRC3pB Driver Offset again. This time it was nearly railed high. Also DCRC3pD seemed high, adjusted it too. |
| 1501 | Adjust DCRC3pB and DCRC3pD Driver Offsets again. |
| 1510 | Stop data series. |
| 1510 | HV = 69.89 V, V_leak = 2.60 mV |
| 1515 | Dial HV down to 0V using changeHV_70_0.msl |
| 1525 | Bring PuBe source back into lab and place behind shield |
| 1525 | Flash DCRC1&3 LEDs for 30 seconds |
| 1710 | Fill LN2 cold trap full. |