| | Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 |
| 0910 | Tower = 33.1 mK, Main Bath = 33.3% |
| 0910 | Move PuBe neutron source into lab. |
| 0915 | Fill LN2 cold trap |
| 1220 | Measure the s/c falloff QET biases of all 6 channels, to the nearest 0.1 uA, and compare to the May 24 table. In order the difference in the falloff current between now and the standard is 0.05/-0.35/-0.15/-0.45/-0.20/0.05. So on average they are about 0.2 uA smaller - which indicates slightly elevated parasitic power. |
| 1230 | Begin 30 minute bake with DCRCs 1&2 |
| 1325 | Start LHe transfer (MB = 27.0%) |
| 1354 | Tower/MC/Coldplate = 33.7/30.1/192 mK, Still = 1.21 K / 0.110 mbar, G1/G2 = 220/201 mbar, 1K Pot = 1.642 K / 20.0 mbar. |
| 1440 | Modify setup so that DCRC4 is now included and set to be timing master. Check that the timing link is working by setting a high trigger on DCRC1pA and using the pulse viewer - all 6 channels show pulses at the correct place so timing link seems to work between DCRC1&2 at least (harder to check DCRC4, Anthony will need to verify that there's a coincidence peak). |
| 1455 | Set all channels to standard QET biases and driver gains. Then fine-tune driver offsets to get baselines very close to -0.80 V, then we can do a quick check to see if they change when we apply bias. |
| 1515 | Dial HV up to 65 V |
| 1525 | Dial down HV, targeting Vdetector=50 V. (Currently HV = 65.13 V, Vtest = 6.22 mV → Vdetector = 62.6 V) |
| 1530 | End LHe transfer (MB = 92.5%) |
| 1540 | HV = 51.39 V, Vtest = 3.38 mV → Vdetector = 50.03 V |
| 1550 | Baselines are elevated somewhat since before the biasing, in order 0.05/0.0/0.0/0.1/0.1/0.1 V. |
| 1610 | Measure the s/c falloff QET biases of all 6 channels, to the nearest 0.1 uA, and compare to the May 24 table. In order the difference in the falloff current between now and the standard is -0.35/-0.75/-0.55/-0.75/-0.40/-0.25. So on average they are about 0.5 uA smaller, indicating elevated parasitic power compared to before the biasing. |
| 1230 | Begin 30 minute bake with DCRCs 1&2 |
| 1614 | Start 2 1-hour data series of 1-sided 50V HV coincidence data with Frontend Gain = (15/15/5)/(3/4/4), OG = 4/2, QET biases = 30 column from table from May 24, with 1000 beginning randoms, no flashing, and a 500ADC bin threshold trigger on DCRC4 pA (external trigger). Running OR trigger of NaI detectors with PuBe source on west side of shield. NaI detector C has 311 mV threshold and detector B has 288 mV threshold |
| 1615 | HV = 51.39 V, Vtest = 3.23 mV → Vdetector = 50.09 V. Will adjust it a bit down. |
| 1620 | Check data with BatViewer, looks OK except DCRC2pA, one of the unconnected channels, is railed high instead of railed low. Prefer railed low for BatViewer purposed. So adjust driver offset. |
| 1630 | HV = 51.30 V, Vtest = 3.16 mV → Vdetector = 50.03 V. |
| 1645 | Fill LN2 cold trap bath |
| 1740 | stop run (a little early) and turn down HV |
| 1740 | retrolog (Anthony) 1800s bake |