2017/05/23 (Tuesday)
| Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 | |
| 0920 | Tower = 33.6 mK, Main Bath = 28.9%. |
| 0930 | Noticed that DAQ programs were off since DAQ work from last night. When I turned them back on the tower temperature decreased to about 32.9 mK, the usual base recently. So maybe one of the DCRCs had its heater on or something. |
| 0945 | Finish IbIs on DCRC2pD/DIB4pD/Side1pF. Repeat of yesterday. I found that that the DCRC1 channels and two of the DCRC2 channels (pB & pC) had QETbias*prefactor values near 30 uA, which is what they were set to back on April 28 - except for this channel, DCRC2pD/Side1pF, which has a value close to 35 uA now. |
| 1145 | Fill LN2 cold trap bath. |
| 1227 | Tower/MC/Coldplate = 33.0/29.5/193 mK, Still = 1.26 K / 0.110 mbar, G1/G2 = 220/210 mbar, 1K Pot = 1.676 K / 24.0 mbar. Main Bath = 23.8%. Boil off rate: slow mode (Predicted level: 23.8%) |
| 1236 | Start LHe transfer (MB = 23.2%) |
| 1322 | End LHe transfer (MB = 92.6%) |
Preparing for another QET bias scan to study dP/dI. From the IbIs measurements of today and yesterday the table below gives QET bias settings to achieve various dP/dI values:
| QET bias settings for different dP/dI [μA] | ||||||
|---|---|---|---|---|---|---|
| QETbias * prefactor [μA] | ||||||
| channel | 30 | 25 | 20 | 15 | 10 | 5 |
| DCRC1pA/DIB1pA/Side1pE | | | | | | |
| DCRC1pB/DIB1pB/Side1pB | 139.3 | 138.1 | 137.05 | 136.25 | 135.55 | 135.1 |
| DCRC1pC/DIB1pC/Side1pD | 126.65 | 125.6 | 124.7 | 123.85 | 123.3 | 122.95 |
| DCRC2pB/DIB3pC/Side1pA | -117.8 | -116.45 | -115.3 | -114.35 | -113.6 | -113.15 |
| DCRC2pC/DIB4pC/Side1pC | -150.05 | -149.15 | -148.35 | -147.65 | -147.15 | -146.7 |
| DCRC2pD/DIB4pD/Side1pF | -146.2 | -145.35 | -144.7 | -144.15 | -143.75 | -143.45 |
| corrected version here | ||||||
| Note: | I made a calculation error in the IbIs for DCRC1pA. So the above table is incorrect for that row. Below are corrected Ib*pf values for DCRC1pA. |
|---|
| DCRC1pA/DIB1pA/Side1pE | |
|---|---|
| Qb [μA] | Qb*pf [μA] |
| 128 | 32.2 |
| 127 | 27.5 |
| 126.05 | 22.4 |
| 125.35 | 17.5 |
| 124.75 | 12.5 |
| 124.35 | 7.92 |
To get the pulses within range the driver offsets must be adjusted. Below are appropriate driver offset settings (under current conditions) corresponding to the settings above:
| Driver offset settings for different dP/dI [μA] | ||||||
|---|---|---|---|---|---|---|
| QETbias * prefactor [μA] | ||||||
| channel | 30 | 25 | 20 | 15 | 10 | 5 |
| DCRC1pA/DIB1pA/Side1pE | -0.36 | -0.38 | -0.4 | -0.42 | -0.44 | -0.46 |
| DCRC1pB/DIB1pB/Side1pB | 0.28 | 0.26 | 0.23 | 0.21 | 0.19 | 0.16 |
| DCRC1pC/DIB1pC/Side1pD | 0.25 | 0.23 | 0.2 | 0.18 | 0.16 | 0.13 |
| DCRC2pB/DIB3pC/Side1pA | 0 | 0.01 | 0.03 | 0.04 | 0.05 | 0.07 |
| DCRC2pC/DIB4pC/Side1pC | -0.55 | -0.53 | -0.52 | -0.5 | -0.48 | -0.47 |
| DCRC2pD/DIB4pD/Side1pF | -0.22 | -0.21 | -0.19 | -0.18 | -0.17 | -0.15 |
| 1410 | Edited sequence script QETbias_sweep.msl to go through the above settings, starting at the Ib*pf = 30 values, taking 2 hours of data at each setting. Also need to consider trigger threshold. Recently we've triggered on DCRC1pA with a threshold of 20. To keep a theoretically constant energy threshold we should have threshold*(Ib*pf) = constant. So for Ib*pf = 30,25,20,15,10,5 we'd set thresholds 20,24,30,40,60,120. |
|---|---|
| 1500 | |
| 1510 | Start 12 1-hour data series (start #6640) of 1-sided 0V data with Frontend Gain = (15/15/5)/(5/6/4), OG = 4/2, QET biases set as in table, starting at Ib*pf=30 and stepping down to 5 with 2 hours at each setting, with 1000 beginning randoms, no flashing, and a 20/24/30/40/60/120 ADC bin threshold trigger on DCRC1 pA (Side1 pE). DCRC4 is still set up to read NaI triggers but isn't relevant for this sequence. |
| 1615 | Stop sequence because DCRC2pC is railed. Relocking fixed it, but who knows if it will remain stable. |
| 1619 | Start 12 1-hour data series (start #6640) of 1-sided 0V data with Frontend Gain = (15/15/5)/(5/6/4), OG = 4/2, QET biases set as in table, starting at Ib*pf=30 and stepping down to 5 with 2 hours at each setting, with 1000 beginning randoms, no flashing, and a 20/24/30/40/60/120 ADC bin threshold trigger on DCRC1 pA (Side1 pE). DCRC4 is still set up to read NaI triggers but isn't relevant for this sequence. |
| 1815 | Fill LN2 cold trap. |