2017/03/06 (Monday)

	Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33
	HV = 0, bake overnight, Tower = 480 mK during bake, began cooling at 08:26
0945	Tower/MC/Coldplate = 33.9/31.3/196 mK, Still = 1.3 K / 0.110 mbar, G1/G2 = 250/250 mbar, 1K Pot = 1.684 K / 26 mbar, Main bath = 70.6%. Boil off rate: a bit faster than slow mode (predicted level: 72.4%).
0955	Fill LN2 cold trap bath
1000	Measure background event rate by counting pulses in 20 50-ms traces. Count 89 events in 1 second = 89 Hz.
1015	Erect shield walls around fridge on West and East sides. Measure background rate: count 59 events in 1 second = 59 Hz.
1145	Install top corner lead shield pieces (without poly). Measure background rate: count 56 events in 1 second = 56 Hz.
1355	Remove lead counterweight sheets from bottom of shield. Measure background rate: count 50 events in 1 second = 50 Hz. Looks like bottom lead doesn't help much.
1440	Install North shield wall, lead only, no poly. Measure background rate: count 35 events in 1 second = 35 Hz.
1545	Install South shield wall, lead only, no poly. Measure background rate: count 24 events in 1 second = 24 Hz.
1606	Start sequence of 15, 1-hour data series of 1-sided 0V HV data with Frontend Gain = (15/20/20)/(-/4/3), OG = 8/3, with 1000 beginning randoms, no flashing, and a 35ADC bin threshold trigger on DCRC1 pA
1729	Data looks good so far.
1749	Fill LN2 cold trap full.