| | Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 |
| | Overnight bake was stable at 480 mK, ended at 0518 |
| 1239 | Tower/MC/Coldplate = 33.8/31.1/194mK, Still = 1.28 K / 0.110 mbar, G1/G2 = 249/222 mbar, 1K Pot = 1.691 K / 28 mbar, Main bath = 62.0%. Boil off rate: faster than slow mode (predicted level: 66.3%). |
| 1243 | Fill LN2 cold trap |
| 1244 | Tweak 1K pot needle valve |
| 1346 | 1K pot pressure = 30 mbar |
| 1349 | Prebias detector to HV = 15 V |
| 1405 | Reduce HV to 10V |
| 1407 | Start sequence of 16, 1-hour data series of 1-sided 10V HV data with Frontend Gain = (20/20/5)/(6/4/3), OG = 8/4, with 1000 beginning and ending randoms, no flashing, and a 35ADC bin threshold trigger on DCRC1 pA |
| 1409 | HV = 10V, V_leak = -0.3 mV, V_crystal = 10.1 V |
| 1419 | Notice DIB2 PC railed. |
| 1429 | Recovered DIB2 PC. |
| 1758 | Pulses still look good |