| | Setup: DIB1/3/4 → 3.2 MHz filters 3/1/2 → cable 3/1/2 →gender changer 3/1/2 → HVConn 1/3/2 → HV 1/2 → DCRC55/DCRC33 |
| | Took data overnight, DIB2 PC was railed the whole time. |
| 0910 | HV=9.99V, Vleak = 0±0.1 mV, V_crystal = 9.99±0.04 V |
| 0912 | Tower = 33.6 mK, Main bath = 64.6% |
| 0925 | Fill LN2 cold trap full |
| 0935 | Tower/MC/Coldplate = 33.3/30.6/195mK, Still = 1.21 K / 0.110 mbar, G1/G2 = 235/205 mbar, 1K Pot = 1.691 K / 30 mbar, Main bath = 64.0%. Boil off rate: faster than but close to slow mode (predicted level: 67.5%). |
| 1430 | Ground HV and start 1 hour bake. |
| 1603 | Tower temp = 35.5 mK Prebias HV to 15V |
| 1618 | Reduce HV to 10V |
| 1624 | Start 12, 1-hour data series of 10V HV data with Frontend Gain = (20/20/5)/(6/4/3), OG = 8/4, with 1000 beginning and ending randoms, no flashing, and a 35ADC bin threshold trigger on DCRC1 pA |
| 1625 | Hv = 10 V, V_leak = 0.2 mV, V_crystal = 9.91 V |
| 1748 | Fill LN2 cold trap full. |