2016/12/06 (Tuesday)

Previous Day

	Setup: DIB1/3/4 → 3.2 MHz filters → cables 1,2,3 → HV board inputs 1,3,2 → HV board outputs 1,2 → DCRC55(1)/50(3)
0845	Main bath = 69.4%
0915	Finish microIbIs on all 6 channels. But I notice that the SQUID settings are not staying constant! The values I set yesterday after switching to HV setup seem to keep reverting to some other values, according to the DCRC Control interface. Annoying.
1105	We are still having the problem that when we reset values using the DCRC Control browser page, then close and reopen the edit window, the values revert to previous values. Investigating further, it seems that the revert values are not actually the settings on the DCRC. They seem to be false values. This can be seen for example in the QET bias of DCRC1pB. It should be 185, but the edit window reverts to 190. But viewing the trace, it appears that the baseline is consistent with the 185 setting - you have to manually set it to 190 to see a shift.
1115	The ODB interface did not have the same problem: the values seemed to be the most recently entered, not reverted to something else. Tried refreshing the DCRC Control window, and this seems to have fixed the problem.
1140	Finish microIbIs on all channels. There were some anomalies in the earlier one today, things seem more consistent now.

Comparison of micro-IbIs results

Standard values in 2-sided mode compared to yesterday's IbIs and today's micro-IbIs

Notes:

New HV results are in general inconsistent with 2-sided values
The lower values imply lower parasitic power than for the 2-sided standard (metastable state?)
DCRC1pB had a bad IbIs curve in 2-sided data, so no basis for comparison
DCRC3pB is probably not reliable now due to SQUID jumping.
- Note that this is Side1pA which was DCRC2pC in 2-sided mode

1215	Try an IbIs curve for DCRC3pB again, this time with driver gain only 1x instead of 2x. There are still SQUID jumps. But it seems fairly easy to remove the jumps and patch the curve together.

DCRC3 pB IbIs, driver gain = 1x

Note that the same shift value is used for the high- and low-bias regions to bring them in line with the middle, and it seems to work in both cases

1235	Restore driver gains to standard 8x and adjust driver offsets for data taking.
1240	Experiment with DCRC3pD trigger threshold, looks like 50 basically works. Will set up for 45.
1240	Change ODB→Logger→Subrun_duration to 60 (1 minute dumps), back from 600 (10 minute dumps) setting on Sunday.
1245	Start a sequence 1-hour series of 0V data with Frontend Gain = 5 except DCRC3pB=1, OG = 8, with 1000 beginning randoms, with no flashing in between series, and a 45ADC bin threshold trigger on DCRC3 pD.
1250	Check with BatViewer, data looks good, timing link is working, there are a fair number of noise triggers so the threshold seems to be low enough.
1345	Tower/MC/Coldplate = 33.2/36.0/225 mK, Still = 1.3 K / 110 μbar, G1/G2 = 190/185 mbar, 1K Pot = 1.69 K / 26 mbar. MB = 62.1%.
1350	Fill LN2 cold trap bath.
1434	Stop data. Something went wrong 13 minutes into the second series, _1345. All the traces seemed semi-railed… then at 19 minutes in they looked ok except that DCRC3pC was railed.
1440	Unrail DCRC3pC
1450	Plug in HV power supply to HV board, at zero volts. Unfortunately this causes almost all channels to rail. DCRC3pB has strong 60Hz noise. After unrailing channels, most are not showing pulses, suggesting they may have fallen into superconducting.
1500	Did some snapping, all channels seem to be showing pulses again at their standard QET biases (except DCRC3pB is mostly 60Hz noise)
1525	Perform microIbIs, for all except DCRC3pB, all are still pretty close to earlier today.
1530	Dial HV up to 35 V for pre-bias, then wait 5 minutes.
1540	Dial HV back down to 30 V after prebias. Vtest = 0.6 mV.
1600	Perform semi-complete IbIs on DCRC1 pA. It is very close to yesterday's IbIs, almost no shift.
1605	Dial HV back down to zero in preparation to flash detector before data taking
1605	Flash detector. Tower rises to 0.5 K then starts to fall. As tower begins to cool increase HV to 35 V prebias, wait 5 min or so, dial down to 30 V.
1620	Notice that the bad 60Hz noise on DCRC3pB seems to have disappeared.
1630	Tower down to 33.9 mK, close to base
1635	Start a sequence of 15 1-hour series of 30V data with Frontend Gain = 5, OG = 8, with 1000 beginning randoms, with no flashing in between series, and a 50ADC bin threshold trigger on DCRC3 pD. Vtest = 1.8 mV. DCRC3pB is intentionally railed since it is dominated by 60Hz noise. Aborted.
1640	BatViewer shows that the threshold is too low, almost all triggers are noise, pulses are typically not in the right place. Try higher.
1641	Start a sequence of 15 1-hour series of 30V data with Frontend Gain = 5, OG = 8, with 1000 beginning randoms, with no flashing in between series, and a 60ADC bin threshold trigger on DCRC3 pD. DCRC3pB is intentionally railed. Aborted.
1645	It still seems to be a bit too low. Try raising the threshold again.
1649	Start a sequence of 15 1-hour series of 30V data with Frontend Gain = 5, OG = 8, with 1000 beginning randoms, with no flashing in between series, and a 70ADC bin threshold trigger on DCRC3 pD. DCRC3pB is intentionally railed. Aborted after 20 min
1705	Very many of the pulses are ADC saturated. This is probably not ideal and will only get worse as we increase the HV. We've decided to lower the driver gains.
1710	Change driver gains to x4 and readjust driver offsets to get the baselines low-ish
1714	Start a sequence of 15 1-hour series of 30V data with Frontend Gain = 5, OG = 4, with 1000 beginning randoms, with no flashing in between series, and a 35ADC bin threshold trigger on DCRC3 pD. DCRC3pB is intentionally railed.
1723	Traces look pretty good in Batviewer. Around 50% of the traces have an ADC railed channel, but hopefully this is good enough to get the 10keV peak.
	next day noticed that DCRC1pC railed 17 minutes into the first dump, 1206_1713 (at event 1563). It was railed throughout the rest of the sequence.
1724	Measure leakage: Vtest=1.8mV. So Vdetector=29.2 V.
1725	Fill LN2 cold trap full.

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