| | Setup: DIB1/3/4 → 3.2 MHz filters → cables1/2/3 → DCRC55(1)/33(2)/50(3) |
| 0840 | Tower/MC/Coldplate = 33.4/34.7/237 mK, Still = 1.4 K / 110 μbar, G1/G2 = 194/171 mbar, 1K Pot = 1.70 K / 30 mbar. MB = 65.7%.
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| 0840 | Fill LN2 coldtrap full. |
| 0948 | Trying to bring DCRC1 PhB,C,D back by snapping, got all the DCRC1 channels back, PhC needed a shift in QET bias up to 192uA in order to get away from oscillation (about 10kHz). Note I have not ZAPPED after power cycle but the pulses seem to be pretty good, I'll try not doing it. |
| 1100 | I hacked the trigger code so that DCRC1 will not issue any triggers this is because the hardware was issuing spurious triggers |
| 1107 | Start sequence of 6 one-hour data series of 0V data with Frontend Gain = 5/2/5, OG = 8/3/8, with 2000 beginning randoms (because of increased pileup from higher source rate), with no flashing in between series, triggered with NaI coincidence setup (front-to-back coincidence) using DCRCX (DCRC4) PhA, with DCRC1 triggers disabled. |
| 1124 | started coincidence hardware counter |
| 1642 | Fill LN2 coldtrap full. |
| 1700 | return 88Y source to safe |
| 1728 | Setting up overnight running, trigger on DIB3 PhD because that is PFS1, Use same trigger threshold as before, 70 samples |
| 1736 | for some reason pulses are railed but they seem to be fine throughout the last series of the day 07161121_1608 |
| 1817 | Start sequence of 15 one-hour data series of 0V data with Frontend Gain = 5/2/5, OG = 8/3/8, with 1000 beginning randoms (because of increased pileup from higher source rate), with no flashing in between series, trigger on PhD of DCRC3 (PFS1) at 70 samples |