| 1127 | Release pressure from main bath |
| 1141 | Release pressure from main bath |
| 1242 | 88Y source out of safe and in lead castle behind cryostat |
| 1300 | set up coincidence gating with two NaI detectors behind and in front of cryostat |
| 1310 | the ODB thought the DCRC1 was a RevC not RevC.1 like it is, it must have spontaneously changed |
| 1311 | some kind of error with the DCRC UI frontend while editing detector settings, something about a “child node” I just pushed “OK” |
| 1312 | set up the DCRCs with the Nov 15 QET bias settings and offsets so that baselines are near -1V approximately |
| 1314 | finding that when triggering on DCRC4 at low rates not all triggers seem to be the negative-going TTL signal, some seem to be noise and at the rate that I'm triggering the noise seems to be a comparable component to the real triggers, why is this happening? Does the SQUID tuning GUI naturally trigger at some low rate? I don't think so. I'm sure that randoms are turned off |
| 1318 | to further diagnose this tried to set the master/slave bits correctly (no effect), reset the timing link manually (no effect), reconfigure the physical cable for the trigger in (no effect), and restart the frontends several times (no effect) |
| 1320 | noticed that DCRC1 PhC seems to be in an unstable part of the transition because there is clear ringing on the pulses, try to tweak QET bias until better |
| 1325 | bringing the channel down just a little lower in the transition to DIB 1 PhC QET bias of 182 uA seemed to ease the oscillation a bit, going up in QET bias quickly brought on pure harmonic noise at about 10 kHz |
| 1327 | test data taking in this mode |
| 1331 | still noticing a lot of triggers that were not because of the TTL pulse on DCRC4, did some manual RT commands on DCRCs 1,2,3 and found that DCRC 1 was issuing some kind of trigger periodically and the others were not issuing any I also noticed that one of the boxcar parameters on DCRC 1 was different than the others, changing that back to 5/16 now instead of 4/16 |
| 1341 | checked the trigger enable bits on all DCRCs directly from telnet, this is register 0x17, they all appear to be correct, in particular DCRC1 has it set to 0, so I don't understand why it puts something in the trigger buffer then |
| 1352 | I didn't want to, but I had to power cycle DCRC1 due to the above trigger problems. The channels seem to be railed and the triggers are still being issued by DCRC1. When I disable DCRC1 in the DAQ the trigger seems to work like I expect |
| 1357 | I was able to snap DCRC1 PhA back into transition, I don't know if the properties changed but it appears to behave similarly after power cycle. I won't try the rest because without solving the trigger problem above the data I take would be bad |