2016/11/03 (Thursday)
| Setup: DIB1/3/4 → 3.2 MHz filters → cables 1,2,3 → HV board inputs 1,3,2 → HV board outputs 1,2 → DCRC55(1)/50(3) | |
| 0815 | Tower/MC/Coldplate = 32.7/35.4/216 mK, Still = 1.36 K / 120 μbar, G1/G2 = 165/150 mbar, 1K Pot = 1.71 K / 36 mbar. MB = 74.2%. Boiloff rate: a bit worse than slow-mode |
| 0820 | Return Cf source to safe. |
| 0825 | Fill LN2 cold trap bath. |
| 0850 | Check event rate now that half of the shield is up. Count pulses above noise in DCRC1pA. In 20 50-ms traces (1 second) count 51 pulses, so 51 Hz background rate (improved from previous which was around 80 Hz). This gives a 36% rate of pulseless traces for 20-ms traces, only about 8% for 50-ms traces. |
| 1031 | 07161103_1032 (?) SC dIdV data set. 18mVpp, 200Hz, 13.1072ms = 16384bins. All channels have triangle wave on them. |
| 1217 | 07161103_1214 (?) Transition dIdV data set. DG=8. 18mVpp, 200Hz, 13.1072ms = 16384bins. All channels have triangle wave on them. See spreadsheet for Ib and all resistance values. DCRCchC railed. Important Point: test signal is 180 degrees difference in phase between DCRC1 and DCRC3!!! retake with following data set: |
| 1226 | 07161103_1224 (?) Transition dIdV data set. DG = 8. 18mVpp, 200Hz, 13.1072ms = 16384bins. All channels have triangle wave on them. See spreadsheet for Ib and all resistance values. DCRC3chC has an interesting feature at the triangle point. All other channels look good. Still unclear how much complex impedance info can be pulled from the triangle wave (e.g. no simple reading off of \beta is available without the square wave) |
| 1252 | 07161103_1252 (?) Transition noise data set. DG = 8. 26.2144ms = 32768bins. Noise data set before putting up the shield. Rate seems manageable with these shorter traces. Will need a lot of randoms though. DCRC1chA suddenly railed, but hopefully caught it so that most of this data is good. |
| 1300 | 07161103_1300 (?) Transition noise data set. DG = 8. 26.2144ms = 32768bins. DCRCchC pulses seem to overshoot – it is as if there is an autozero on this channel. Do not believe that this is TES related, but could be. Not present on other channels, except also a bit on DCRC1chA. Possibly also being introduced by DCRC (obviously there shouldn't be different filtering per channels) |
| 1400 | Building the remaining two walls of the lead/poly shield. Only four layers of poly on the two non-permanent walls because the poly is probably not very important for our purposes. |
| 1500 | Shield is finished except for some top pieces. Check background rate again: counted 20 pulses in 10 100-ms traces, so 20 Hz. |
| 1539 | 52.4288ms noise data: 07161103_1510 :DCRC1chA railed at one point. 07161103_1522 : DCRC1chA railed at one point. 07161103_1526 : carefully monitored all channels and should be good |
| 1725 | Main bath (MB) = 60.6% |
| 1730 | Fill LN2 cold trap bath |
| 1936 | After 1.5hrs of difficulty with TESs, finally all of side 1 is biased at ~50mOhm (details, including Rp/Ib values in spreadsheet) Now for some data: 07161103_1937 noise data set with 3.2768ms = |
| 2032 | Pulse data. Many dumps. Intended for finding the 10keV line and measuring the absolute phonon calibration. 07161103_2017 3.2768ms = |
| 2158 | End data set above with 90 dumps. Do a check of bias powers and take a noise data set : 07161103_2158 |
| 2237 | Trouble with oscillations and waveform glitches (presumably DCRC induced). Resolved these problems and have more pulse data in dataset here: 07161103_2236 . Plan to leave this data set going overnight. Note: DCRC1chC has some serious jaggedness: phase separation? ended series due to this. start another data series 24 dumps in this one. |
| 2303 | jaggedness could not be fixed on DCRC1chC. It simply exists between the TES oscillation regime and superconducting. Leaving with pulse data going: 07161103_2314 |