2016/08/24 (Wednesday)
| Setup: iZIP mode, DIB1/2/3 → 3.2 MHz filters → cables → DCRC55(1)/33(2)/50(3), Tower has been cooled below Al transition with mu-metal shield 37.8cm below standard position | |
| DCRCs powered overnight. Pumping on IVC with turbo pump overnight. Baked detector for 12 hours overnight, Tower at 0.4 K until 05:35. | |
| 0848 | Tower/MC/Coldplate = 38.3/32.3/154 mK, Still = 1.32 K / 90 μbar, G1/G2 = 185/176 mbar, 1K Pot = 1.53 K / 5.0 mbar, MB = 74.4%. Boiloff rate: good. Yesterday pressure was released at 5min, 30min, and 63min after a 92.0% fill. |
| 0852 | Fill LN2 cold trap full. |
| 0900 | Check phonon channels, adjust one driver offset, all have baselines around -0.6 to -0.8 |
| 0900 | With DIB2 FETs turned off, Start three sets of 30min background series at -6/+6 V with FG=5/2/5, OG=8/3/8, with 1000 initial randoms, 1000 ending randoms. Trigger on DIB1 phA with threshold of 30ADC bins, with 150 us pileup cut window. |
| 1300 | Check for breakdown with standard iZIP DCRC biasing. |
| using DIB3pD, looked for jagged “breakdown noise”. Also looked for shift in baseline |
| bias [V] | breakdown noise | baseline shift [V] |
|---|---|---|
| +8/-8 | none | +0.03 |
| +10/-10 | mild | +0.08 |
| +12/-12 | moderate/high | +0.26 |
| -8/+8 | none | |
| -10/+10 | none | |
| -12/+12 | none | +0.01 |
| typically baseline shift was higher at first, then relaxed |
||
note that in Run 54 it was observed that breakdown symptoms were worse after a flash…
| 1325 | Flash detector for 30 seconds |
|---|---|
| 1400 | Tower has cooled to 38.7 mK, repeat above tests monitoring DCRC2pD: |
| bias [V] | breakdown noise | baseline shift [V] |
|---|---|---|
| +8/-8 | slight | +0.05 |
| +10/-10 | moderate/high | +0.12 |
| +12/-12 | moderate/high | +0.32 |
| -8/+8 | none | 0 |
| -10/+10 | none | |
| -12/+12 | none | +0.01 |
| overbias to +13/-13, then | ||
| +12/-12 | moderate | +0.11 |
| set back to 0/0, then | ||
| +12/-12 | moderate | +0.16 |
| 1430 | Turn off trigger, tower, and DCRC programs on MIDAS, disconnect telnet DCRC sessions, unpower DCRCs. |
|---|---|
| 1440 | Set up HV mode, DIB1/2/3 → 3.2 MHz filters → nothing/disconnector board/remapping board → HVside2board → DCRC55(1)/50(3). Disconnector board has all charge lines disconnected. |
| 1440 | Tower has fallen to 37.2 mK |
| 1445 | Power up DCRC1&3 and initiate telnet sessions |
| 1445 | On ODB, disable DCRC2, and reset phonon settings on DCRC3 to apply the settings used for the same phonon channels with the previous iZIP mapping. DCRC 3D/2C/2D are now mapped to DCRC 3B/3C/3D. |
| previous | new | |||||
|---|---|---|---|---|---|---|
| channel | lockpoint | SQ bias | QET bias | lockpoint | SQ bias | QET bias |
| DCRC3B | -3.72 | -81.2 | 107 | -4.5 | -82.6 | 130 |
| DCRC3C | -1.7 | -70.0 | 86 | -2.57 | -79.2 | 125 |
| DCRC3D | -4.5 | -82.6 | 130 | -2.76 | -93.5 | 97.7 |
| Don't forget to change these back if/when we revert to iZIP mode |
| 1507 | Zapping squids. |
|---|---|
| 1550 | Plug in 1kV power supply to HV board, set to ~0 V. Rails the three DCRC3 phonon channels. Restore these with relocks. DCRC3pB (the one that crosses ground planes) has ugly noise, high frequency with an envelope structure |
| 1600 | Apply HV while monitoring DCRC1pC. After each change in HV wait about one minute to record leakage voltage and phonon channel behavior. |
| HV [V] | Vleak [mV] | Baseline [V] | noise/pulses | Vcrystal [V] | Baseline shift [V] |
|---|---|---|---|---|---|
| 0 | 0 | -0.75 | no noise | 0 | 0 |
| -10 | -11.6 | -0.72 | no noise | -4.896 | 0.03 |
| -15 | -17.8 | -0.54 | noise first seen | -7.168 | 0.21 |
| -20 | -23.9 | -0.1 | noisy | -9.484 | 0.65 |
| -25 | -29.5 | 0.57 | noisy | -12.02 | 1.32 |
| -15 | -16.7 | -0.74 | no noise | -7.652 | 0.01 |
| -25 | -30.8 | 0.48 | noisy | -11.448 | 1.23 |
| -20 | -23.6 | -0.72 | no noise | -9.616 | 0.03 |
| -30 | -36.8 | 0.63 | no pulses | -13.808 | 1.38 |
| -25 | -29.8 | -0.48 | low noise | -11.888 | 0.27 |
| 30 | 37.9 | -0.2 | noisy | 13.324 | 0.55 |
| 25 | 30.2 | -0.72 | no noise | 11.712 | 0.03 |
| 35 | 42.6 | 0.6 | noisy | 16.256 | 1.35 |
| 30 | 35 | -0.67 | no noise | 14.6 | 0.08 |
| 40 | 49.5 | 0.63 | no pulses | 18.22 | 1.38 |
| 35 | 41.7 | -0.53 | some noise | 16.652 | 0.22 |
- As indicated in the above table, there are distinct improvements with overshooting the bias and then stepping back.
- A baseline shift of more than 0.2 V is always accompanied with some evident breakdown noise. We could use a 0.2 V baseline shift as an indicator of breakdown.
- Today we were able to achieve HV-mode crystal biases of -9.6 V and +14.6 V without breakdown.
| 1650 | Switch back to setup: iZIP mode, DIB1/2/3 → 3.2 MHz filters → cables → DCRC55(1)/33(2)/50(3) |
|---|---|
| 1655 | Begin 12-hour bake |
| 1734 | End LN2 coldtrap full. |