UMN CDMS Wiki archive
start › cdms › k100 › run_diary › 20150915

2015/09/15 (Tuesday)

previous day

Current setup: HV mode, DIB1/2/3 → cables → 3.2 MHz filters → HV box 1/2 → DCRC50/55.
Overnight: idle, no source
0935 Fill LN cold trap Dewar
0940 Tower/MC(H35)/MC sensor/Cold Plate = 30.6/24.3/43.4/152 mK, Still = 1.27 K / 0.080 mbar, G1/G2 = 150 mbar, 1K Pot = 1.72 K / 24 mbar
1015 Repeat yesterday's standard-bias baseline versus HV test for negative HV:
HV1pA baseline (std. QET bias, 93.2 μA)
HV (V) I_leak (nA) Baseline (V) notes
0 -0.1 0.065
-14 -24.1 0.065
-15 -25.3 0.065
-15.4 -26 0.08
-16 -26.4 0.08
-16.4 -26.9 0.1
-16.8 -28.8 0.12
-17.2 -29.1 0.13
-17.6 -30 0.15
-18 -30.4 0.18
-18.4 -30.9 0.22
-18.8 -32 0.27
-19.2 -32.9 0.32
-19.6 -33.6 0.34 pulses almost gone
-20 -34.4 0.34 pulses completely gone
1030 At HV = -31 V / -56.7 nA (near max for small supply), Tower temperature increases from 30.5 to 31.4 mK.
1040 Disconnect DCRCs and remove HV box.
1045 Connect DCRCs, zap, apply settings.
Current setup: iZip mode, DIB1/2/3 → cables → 3.2 MHz filters → → DCRC55/33/50.
1114 Main bath = 61.0%
1130 All frontend gains set to 1, output gains still set to 3.
1208 Midas tests of zapping and flashing.
1600 Commence Midas flashing tests.
1620 Set up phonon channels with DCRC 55/33/50 having Frontend Gain= 5/2/5 and Output Gain= 3/3/3. New driver offsets listed below:
A B C D
DCRC55 0.116 0.024 0.020 0.030
DCRC33 0.024 0.030 -0.026 -0.042 0.014
DCRC50 -0.030 0.030 0.018 -0.028
1630 Set phonon thresholds:
A B C D
DIB1 40 35 45 45
DIB2 30 60 25 30
DIB3 45 45 45 45
1640 DIB2pB keeps railing requiring a relock. Looking at the modulation curve, see that the SQUID looks over-biased. Zero all SQUID values and zap SQUIDs.
1655 DIB2pB still railing every ~60s. Modulation curve looks the same. Power cycle.
1711 DIB2pB not railing as often after power cycle, but the modulation curve still seems to have resonances.
pB railed, but changing driver offset from 0.030 to -0.026 brings it back without a relock.
1730 DIB2pB hasn't railed in 20 minutes with the new driver offset. Create new MultiDAQ files for new gains and driver offsets at 0V, -/+4V, and -/+2V.
1740 Set DAQDAQ2 to take 4 cycles of 15 minute data series of first -/+2V then -/+4V. Frontend gain set to 5/2/5, Output Gain set to 3/3/3. OR trigger across all phonon channels. 1000 initial randoms and 2000 events/file. 30s flash and 30min cooldown in between series.
1745 Start data series. No external source, alternating -/+2V and-/+4V.
1755 Fill LN2 cold trap full.

next day