2015/07/12

previous day

Timing Link Tests

Trying to think of a way to understand how the timing link noise comes in, and perhaps ways to mitigate it. Basically I started out wanting to do something like:

1. get good pulses on DCRC 33 (DIB 1, w/ 100 MHz filter)
2. plug in another board

Trying to do 1), I plugged in DCRC 33 (after all were unplugged), and initiated a ZAP. During the zap the registers read:

Loaded the file dcrc33_dib2_0V_QET_20150630.xml to all the channels, and changed settings to what they were found to be for this DCRC on DIB1. Those settings came from the run diary on 07/10/15, it seems those settings pertain to NOT having the filter. I proceeded with these anyway, even though we now have the filter on, I don't think we measured how IbIs is affected with the 100 MHz filter.

Fumbled around trying to get the triggers working, and realized that the “memory write” was not enabled so I wrote 0x21 to the register 0x15. Noted that phD has a very large rope-like noise (so I grounded it), when Matt came in today he noted that this was probably because of a high frontend gain (near 7) which is known to introduce noise.

In this configuration I found that the pulses looked OK, maybe some noise on the tails and phC looked more noisy by a factor of 2-3 (although this could be because of high driver gain).

Now plug in DCRC 50 on DIB 3, “timing link noise” comes in on DIB 1 immediately, looks like about 4 kHz, 0.25 ms period.

The register values for the just-powered-up DCRC 50 are below.

The register 0x15 value indicates when this DCRC comes on it has no external reference configured, the “VXO” (onboard oscillator) is set to the middle of it's tuning range. When I change the register 0x15 to make the DCRC 50 a slave, this mitigates the noise considerably (timing link cable still not hooked up), but still larger baseline that I might have hoped and some structure is present.

I tried changing the timing link to “external LEMO” but this didn't have any effect. Plugged in the link cable (CAT-5) and set up the link by switching back over to LVDS external input on DCRC 50.

I can see what now looks like a 1 kHz remnants on the tails of pulses, most prominent on channel A.

Started to take a look at the DIB 3 pulses, but remembered that I forgot to ZAP those channels, I tried this without changing the QET or SQUID parameters. This didn't seem to work and somewhere in all of this the DIB 1 pulses also got really strange –> heavily shelved.

I now tried ZAP on DIB 1 without changing the parameters, and still got shelved pulses.

Finally, I ZAPed both DIBs, setting the parameters to zero but not changing the timing link (it's still setup). This resulted in getting DIB 1 back without shelving, but bad noise (still maybe due to the high FG):

I then tried to get DIB 3 back while observing DIB 1. The trigger thresholds were as follows:

Shelving on DIB 1 seemed to appear when I set up phC on DIB 3. Setting the phC QET bias to zero may have mitigated this a bit. Also noticed here that phD was not biased on DIB 3, so I biased it. After that looking at DCRC 50 saw clear shelving on A & D and something brought in (more?) shelving on DIB 1, maybe the biasing of DIB 3 phD. Removing the QET bias of phD DIB 3 didn't improve things, maybe it got into a “bad” state.

I'd say that I haven't shown anything concrete, but it seems (as has been hinted before) that biasing certain channels can affect other DIBs adversely. Also, even when the timing link is “set up” noise that may be from the general timing setup is still present, although the link of the residual noise to the timing setup has not been established firmly.

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