Run 8

After conducting a vacuum leak check and raising the dewar, the leak rate rose to 1E-6 mbar l/s when helium was introduced into the main bath. Puzzlingly, the leak rate fell shortly afterwards with increasing pressure of helium gas in the main bath. Further investigation confirmed a relationship between the leak rate and helium pressure. In other words, lower helium pressures resulted in a higher leak rate. This behaviour indicated that the leak was a result of strain on an indium seal on an IVC caused by evacuating the main bath. It is likely that this was the source of the cold leak witnessed during Run 7.

The leak was isolated to the second indium seal from the bottom by overpressurising the IVC to 1 psi above atmosphere and searching for it with a sniffer probe. Tightening the bolts in this area solved the problem.

Due to a shortage of M3 brass socket head screws, these were only used to bolt SQUET card ZC23 (connected to G9) to the bottom of the tower. Conventional stainless steel screws were used on SQUET card ZC70 (connected to G8). This allowed for direct comparison.

The brass screws have an effect. The modulation curves for SQUIDs A & D are comparible to B & C for G9. Unfortunately, no supplier stocks M3 brass socket head screws, so they will need to be custom ordered.

A summary of data collected is given in Table 2.

Too low of a trigger threshold saturates the Trigger FIFO Buffer. In other words, if the event rate is too high for the buffer to cope with, it fills up and the DAQ triggers randomly. It is likely that the DAQ software is reading from and clearing the buffer too slowly.

This poses a potential problem for the 100 mm crystal tests. Triggering on the charge channels only with a threshold of 12 mV (60 keV line from Am-241 results in a pulse of amplitude 3 mV, or 12 mV after gain of 4 from DCRC) saturates the Trigger FIFO buffer within a few seconds.

During data acquisition, the DAQ software was found to consistently freeze. After some detective work, it was discovered that the point at which it would hang was dependent on the event rate: the lower the event rate, the greater the amount of data that could be acquired. However, the DAQ would always freeze at some point. Forcing the DAQ software to display every waveform it acquired helped a little. Therefore, the trigger threshold had to be raised in order to gather enough statistics from a run.

This problem is unrelated to the one above regarding the Trigger FIFO buffer. Reading back this buffer once the DAQ had frozen showed it to be empty. This problem might occur due to inefficiencies in the DAQ software, as evidenced by the slight improvement in the number of events recorded when the DAQ was forced to display all pulses. This also poses a potential problem with regards to the 100 mm crystal tests.

Establishing the timing link between the DCRCv3 boards is crucial to reducing the noise. However, even with this in place, the DCRCv3 power supply causes modulation in the baseline. This was seen in Run 7. The extent of this can be seen in Figure 1, where a typical charge pulse of energy 130 keV is illustrated.

Figure 1: A typical charge pulse (E = 130 keV)

The axes are in units of ADC bins. The digitiser resolution is 62.5 μV. A 60 keV event would produce a pulse of height 3 mV on the feedback capacitor/resistor. It would be 12 mV at the DCRC output after a gain of four. Therefore, the amplitude of a 60 keV pulse would be approximately 200 ADC bins.

Figure 2: Charge Noise PSDs after first stage amplification

The timing link fails when attempting to lock the phonon channels. After some investigation it was discovered to be caused by stopping the triangle wave. The DAQ software might be writing to a register that it shouldn't. Therefore, the timing link needs to be re-established after locking each channel. This is a minor inconvenience.

Figure 3: Phonon pulses for event displayed in Figure 1

The digitiser resolution is 152.5 μV.

Figure 4: Phonon Noise PSDs normalised to input coil current