Run 7

The performance of the two new DCRCv3 boards is assessed. We struggle to reach a base temperature of 61 mK, perhaps due to oxidisation of the 30 mK stage while it was open between runs 6 and the abandoned 7. Although we are able to take data, the DAQ code is a little buggy, and this is not helped by the difference in LabView versions between Fermilab (version 10) and us (version 9). The charge traces are pretty noisy. Although charge pulse data has been taken at various biases, we are unlikely to be able to analyse it as the current version of cdmsbats cannot fit negative pulses. This problem is due to be fixed soon by incorporating the detector configuration into the DCRC output. We also collected some phonon and charge PSDs using the DAQ software.

On the bright side, these problems are not insurmountable and can be remedied relatively swiftly. Another run should be possible before the 100 mm crystal arrives.

The helium leak finally put a stop to the run as the temperature started to rise steadily. Although we could have warmed up the tower and tried to pump the helium out, the problems with cdmsbats provided an argument against extending the run.

We diagnosed a short to ground on QET return C on stripline #19, which we estimated to lie around 10“ from the ebox socket. This has cropped up in the past, and we incorrectly diagnosed it as a problem with the SQUET card. We couldn't find the short once we opened the ebox connection flange. However, after removing and rescrewing the stripling connector on the ebox, and sealing it up again, the short magically disappeared. It did not make another appearance during the run.

We should investigate this further with regular checks to see if it crops up again. It is possible that there are some defects in the kapton layer between the traces and shield planes. Apart from considering its replacement, we should exchange the bellows that the striplines run through with a more rigid connection, thus reducing the strain imposed on them.

Please see the cold hardware elog for further details:

ZC-23: http://cdms.berkeley.edu/cdms_restricted/elog/SQUET/766
ZC-70: http://cdms.berkeley.edu/cdms_restricted/elog/SQUET/767

Puzzlingly, the FET Tsense +/FET heater - on SQUET card ZC-70 was open at room temperature. Miraculously, it reconnected itself at liquid nitrogen temperatures, and remained connected at 4 K.

As mentioned above, cdmsbats cannot fit to negative charge pulses. The normal work around is to write an ISR file at the time of data collection, which contains the bias value. The cdmsbats package uses this value to normalise the pulse, or in other words inverts the pulse so that it becomes positive. As the DCRC DAQ software does not write an ISR file, there is none available for the data we have collected, thus making it difficult to analyse.

It is intended to incorporate the detector configuration information into the data files written by the DCRC DAQ in the near future. This will happen in tandem with changes to cdmsbats to allow for this information to be read. Together with the high base temperature and helium leak, we decided it would be best to wait until these changes have been implemented before attempting to conduct physics measurements.

We have collected the following charge-only data files:

To give an idea of scale, Figure 1 shows a typical charge pulse of energy 560 keV. The DCRC power supply is the cause of the witnessed modulation in the baseline.

Figure 1: A typical charge pulse (E = 560 keV)

The digitiser resolution is 62.5 μV. A 60 keV event would produce a pulse of height 3 mV on the feedback capacitor/resistor. It would be 12 mV at the DCRC output after a gain of four.

Figure 2: Charge Noise PSDs after first stage amplification