| Status | Run 74 in progress. |
| | Setup: DIB1/2+acc → SL 41/43 → 3.2 MHz filters → cables 2/3 → nothing/motor_board+HV_board → DCRC50(3)/55(1). No lead/poly shield. |
| | Let's try some data with triggering. Specifically we will try triggering on the inner channel. This is q4, which is DIB2qI, which is DCRC1qI. I can never quite remember whether [0] or [1] on the ODB is qI, but I think it's [0]. |
| | Wrote sequences dcrc_bias_p5.msl and dcrc_bias_0.msl to more quickly apply and remove bias to the 4 channels. |
| 1253 | Start 10min series of +5V data (apply bias ~1 minute after starting series), with 1000 beginning randoms, no in-run randoms, trigger DCRC1[0] scanning through thresholds: 140/120/100/80 at 2/4/6/8 minutes. |
| | Checking with BatViewer it looks like this produced constant triggering even at the highest threshold. |
| 1329 | MB = 20.9% |
| 1400 | Mess around a little with triggering, applying 5V bias and watching with the Pulse Viewer. DCRC1[0] trigger (q4, center channel) seems to require 300 or so threshold to avoid constant triggering. But above that mostly it triggers on glitches (channel railing), though there are some pulses. I think noise in DCRC1 is much worse than Run67… |
| 1420 | Zach arrives at lab. |
| 1423 | Tower/MC/Coldplate = 117/32.6/191 mK, Still = 1.47 K / 0.130 mbar / 0 mW, G1/G2= 157/157 mbar, 1K Pot = 1.67 K / 36±2 mbar. |
| 1438 | Begin LHe transfer @ MB = 19.2% |
| 1440 | Begin filling LN2 cold trap dewar. |
| 1451 | Ended LN2 transfer. |
| 1518 | Ended LHe transfer @ MB = 83.6 |
| 1535 | Zach leaves lab. |