2020/08/05 (Wednesday)
- Lab in-person: Zach
- Virtual partner: Matt, Michael
| Setup | Run 73. DIB 1/3/4 → Stripline 43/48/41 → pi-filters 1/2/3 → Cable 3/1/2 → nothing/nothing/accessory_interposer → HV_Conn 1/3/2 → HV 1/2 → DCRCX(4)/DCRC55(1)-master; DCRC33(2) → HV control. DCRCs on overnight. Lead/poly shield erected (4 lead walls, 2 poly walls). |
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| 1250 | Zach body temperature = 99.3. |
| The instability seen in HV yesterday settled down overnight, with HV = 50 mV, Vtest = -0.04 mV. | |
| 0915 | Try stepping down DCRC2/Charge/Bias[0]. It used to be that “zero” was 11.56 but last night I had to increase it to 11.6 to get HV=0. Now it stays at HV=0 all the way down to 11.4. I put it back to 11.56. |
| 0835 | MB = 71.8% |
| 0925 | Start a 60 min series at HV = 15V, drifting 0.0223 V/s, no prebias, CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (0,320,370,0)/(0,360,420,420) uA, Front-End Gains = (3/3/3)/(5/5/5) 1000 BOR randoms, trigger on DCRC1pD threshold = 8 Use sequence HVdrift_pos15V_22p3mVps_multiloop10_nopre_60min.msl |
| 0925 | Tower = 52.4 mK |
| 0925 | Vtest = 0.6 mV, shortly after beginning of drift. Drift seems to start around 14.5V, close to where it should - contrast with last night when it was closer to 17V, because the HV seemed to be off its calibration. |
| 1042 | Vtest = 2.9 mV, HV = 94.7 V, drift ends. Overall Lag Ratio = 77/60 = 1.28, about as high as last time. This seems pretty consistent, but it is high compared to what I expected from 10 second steps (I expected lag ratio 1.10). |
- The rate at which gain falls in this new 15V data suggests increasing the nominal drift rate from 22.3→29.2 mV/s.
| 1235 | Check DCRC2/Charge/Bias[0] to see where it needs to be set for HV=0V: 11.59. Again this is higher than the 11.56 according to the calibration, so maybe it has shifted - hard to say. |
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| 1245 | Write a new sequence to drift from 15V at rate 29.2 mV/s. HVdrift_pos15V_29p2mVps_multiloop10_nopre_60min.msl |
| 1300 | Zach arrives at lab. |
| 1318 | Start a 60 min series at HV = 15V, drifting 0.0292 V/s, no prebias, CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (0,320,370,0)/(0,360,420,420) uA, Front-End Gains = (3/3/3)/(5/5/5) 1000 BOR randoms, trigger on DCRC1pD threshold = 8 Use sequence HVdrift_pos15V_29p2mVps_multiloop10_nopre_60min.msl |
| 1320 | Tower = 53.1 mK |
| 1320 | Vtest = 0.7 mV, shortly after beginning of drift. Drift seems to start around 16.8V, so the calibration seems to have shifted again. |
| Note: actual rampup seems to take 57 seconds. This is done in 15 nominally-1-second steps. So that's about a 3 second lag per step. And the lag during drift seems to also be around 3 seconds per 10-second step, currently. | |
| 1340 | Tower/MC/Coldplate = 53.1/35.1/193 mK, Still = 1.51 K / 0.18 mbar / 5 mW, G1/G2= 488/445 mbar, 1K Pot = 1.64 K / 26±2 mbar. |
| 1402 | Filled LN2 cold trap dewar. |
| 1417 | MB = 62.0% |
| 1405 | Tower temp started rising ~3K over 18min, still rising at 1425. |
| 1425 | Zach leaves lab. |
| 1900 | Zach body temp = 99.4. |
| 1408 | Looks like MIDAS crashed. HV = 86.7 V and flat until 1435, when I noticed the problem. |
| 1438 | Restart MIDAS. Looks like sequence is starting where it left off with 116 steps of the drift left to go (19 minutes or so). |
| 1445 | The sequence is going, and on the ODB I can see that DCRC2/Charge/Bias[0] is changing as it should. But on the HP readout the HV isn't changing. Why??? Keithley readout shows that Vtest isn't changing either. |
| 1453 | Realized that I hadn't started the DAQ programs, so the sequencer was changing the ODB but there was no communication to the DCRCs. Probably should have tried restarting MIDAS without killing the DAQ programs first, that has worked before. Kill MIDAS again, and stop the sequence. We should reset DCRC2/Charge/Bias[0] to a value corresponding to the current bias, then start the DAQ programs, then step down the HV manually - or write a sequence to do it, and end with a flash. |
| 1505 | Write sequence to dial down HV then flash. Except I couldn't start DAQ programs with all DCRCs activated, so I only activated DCRC2 - so the dialdown worked but the flash didn't go yet. |
| 1515 | I was able to start the programs with only DCRC1&4 enabled, no DCRC2. Flash detector. |
| Before the DAQ crash, the HV rose at a pretty regular 23.2 mV/s, suggesting a lag ratio of 1.26 - close to what it has been in the last few runs, though maybe a little lower. | |
| The gain looks level (at least at the beginning) in this series - good. This rate seems OK, as long as the DAQ lag stays the same. |
- Here the positive and negative gains look about the same, but it should be noted that the “+15V” data was actually around +17V due to the shift in calibration.
| 1535 | Finally after messing around with enabling various combinations of DCRCs, finally able to start the DAQ programs with all 3 DCRCs enabled. |
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| 1650 | Write new sequence for positive 20V drifted data using the same nominal drift rate as before, 29.2 mV/s. HVdrift_pos20V_29p2mVps_multiloop10_nopre_60min.msl |
| 1870 | MB = 56.0% |
| 1835 | Turn off Still Heater. This seems to be helping the detector cool. It was above 55 mK, cooling very slowly. Turning off the still heater caused the circulation pressures to fall a lot, and caused the Tower to warm a bit but then to cool, down below 54 mK after 30 minutes and continuing down. |
| 1915 | As the circulation pressures reach a new minimum, the Tower temperature appears to flatten out around 53.6 mK. I guess cool enough to take some more data. |
| 1918 | Start a 60 min series at HV = 20V, drifting 0.0292 V/s, no prebias, CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (0,320,370,0)/(0,360,420,420) uA, Front-End Gains = (3/3/3)/(5/5/5) 1000 BOR randoms, trigger on DCRC1pD threshold = 8 Use sequence HVdrift_pos20V_29p2mVps_multiloop10_nopre_60min.msl |
| 1920 | Tower = 53.6 mK |
| 1920 | Vtest = 0.9 mV, shortly after beginning of drift. Drift seems to start around 19.3V |
| 2024 | Vtest = 3.4 mV, HV = 122.9 V, drift ends. Overall Lag Ratio = 66/60 = 1.10. Well how about that, we're back to the good lag ratio. Likely the drift rate will wind up being too high in this series. |
- Guess is that we need to change drift from 29.2→24.7 mV/s, if this lag ratio continues.
| 2225 | Write sequence to drift from +20V at 24.7 mV/s HVdrift_pos20V_24p7mVps_multiloop10_nopre_60min.msl |
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| 2239 | Start a 60 min series at HV = 20V, drifting 0.0247 V/s, no prebias, CDMS detector: Driver Gains = 1x, DCRC4/1 QET biases = (0,320,370,0)/(0,360,420,420) uA, Front-End Gains = (3/3/3)/(5/5/5) 1000 BOR randoms, trigger on DCRC1pD threshold = 8 Use sequence HVdrift_pos20V_24p7mVps_multiloop10_nopre_60min.msl |
| 2240 | Tower = 53.5 mK |
| 2240 | Vtest = 0.9 mV, shortly after beginning of drift. Drift seems to start around 19.0V |
| 2345 | Vtest = 3.3 mV, HV = 107.9 V, drift ends. Lag ratio = 66/60 = 1.10, good. |
