2019/11/10 (Sunday)
| Setup | DIB1/2/4 → 3.2 MHz filters → cable 1/2/3 → gender changer 1/2/3 → movable source controller/board with external Feedback resistor/nothing → DCRC55(1)/DCRC33(2)/DCRC50(3) |
|---|---|
| 1145 | Fill LN2 cold trap full. |
| 1146 | Tower/MC/Coldplate = 39.3/31.1/191 mK, Still = 1.47 K/ 0.130 mbar / 0 mW, G1/G2= 171/154 mbar, 1K Pot = 1.66 K / 32±2 mbar. MB= 63.6% |
| 1153 | Data taken at -+8V and -+12V yesterday heated the fridge and there was jagged noise in the charge channels. Currently, at 0V, none of the phonon channels are showing pulses and DCRC1QO has terrible, jagged noise. |
| 1202 | Set DCRC1 Q bias = +2V. Noise on DCRC1 QO gets better and there are pulses in the charge signal. Set DCRC1 Q bias back to 0V, the charge pulses remain (Did it really set the bias back to 0?). And now there are phonon pulses in all channels and the baselines are in the right place too. What is going on? |
| 1207 | Set S1/S2 bias = -8/+8 V. Observe jagged, breakdown noise in phonons. Reducing to -6/6 V improves the noise, but the baseline still looks a little jagged. Reduce again to -4/4 V and things look reasonably stable. So we were probably just conducting between the charge and phonon rails at 8V and 12V, which caused the heating. Looks like 4V is a good, safe standard though. |
| 1212 | Ground and flash detector. |
| 1224 | Start 4x S1/S2=(0 V, +4/-4 V, 0 V, -4/+4 V) bias loop of 30 min Bkg data series with edited phonon settings, Driver gain = 1, with 1000 initial randoms, with biased datasets followed by 30s flashes and 30 min cooldowns trigger on DCRC2pA/B/C/D = 8/8/8/8 ADC using sequence qbias_0_pm4_0_mp4_loop.msl |
| Strange temperature patterns in the above sequences: |
- with -4/+4 V, about 10 minutes after applying bias, temperature rises from 38 to 41.5 mK and stays there
- after -4/+4 V, after the flash, with bias at zero, temperature is still elevated at 39 mK
- when +4/-4 V is applied, temperature falls back to base
- Looking at the data, it seems that 10 minutes into a -4/+4 series, it goes into a bad state with breakdown noise in Side1qO (DCRC1qO) and flat phonon traces, so probably heating the crystal and driving the phonon channels normal.
- Setting the bias to zero doesn't fix this, but setting back to +4/-4 V does fix it. (Next day, find that you only need to set Side 1 (DCRC1) to +4 V to fix the bad state.